EP2A15B724C7 Altera Corporation, EP2A15B724C7 Datasheet

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EP2A15B724C7

Manufacturer Part Number
EP2A15B724C7
Description
Manufacturer
Altera Corporation
Datasheet
Features...
Altera Corporation
DS-APEXII-3.0
August 2002, ver. 3.0
Programmable logic device (PLD) manufactured using a 0.15- m all-
layer copper-metal fabrication process (up to eight layers of metal)
High-density architecture
Low-power operation design
1-gigabit per second (Gbps) True-LVDS
current mode logic (PCML), and HyperTransport
Clock-data synchronization (CDS) in True-LVDS interface to
correct any fixed clock-to-data skew
Enables common networking and communications bus I/O
standards such as RapidIO
Level 4
Support for high-speed external memory interfaces, including
zero bus turnaround (ZBT), quad data rate (QDR), and double
data rate (DDR) static RAM (SRAM), and single data rate (SDR)
and DDR synchronous dynamic RAM (SDRAM)
30% to 40% faster design performance than APEX
devices on average
Enhanced 4,096-bit embedded system blocks (ESBs)
implementing first-in first-out (FIFO) buffers, Dual-Port+ RAM
(bidirectional dual-port RAM), and content-addressable
memory (CAM)
High-performance, low-power copper interconnect
Fast parallel byte-wide synchronous device configuration
Look-up table (LUT) logic available for register-intensive
functions
1,900,000 to 5,250,000 maximum system gates (see
Up to 67,200 logic elements (LEs)
Up to 1,146,880 RAM bits that can be used without reducing
available logic
1.5-V supply voltage
Copper interconnect reduces power consumption
MultiVolt
interfaces
ESBs offer programmable power-saving mode
®
TM
I/O support for 1.5-V, 1.8-V, 2.5-V, and 3.3-V
TM
, CSIX, Utopia IV, and POS-PHY
Programmable Logic
TM
, LVPECL, pseudo
Device Family
TM
APEX II
TM
Table
interface
Data Sheet
20KE
1)
1

Related parts for EP2A15B724C7

EP2A15B724C7 Summary of contents

Page 1

... August 2002, ver. 3.0 Features... Altera Corporation DS-APEXII-3.0 ® Programmable logic device (PLD) manufactured using a 0.15- m all- layer copper-metal fabrication process (up to eight layers of metal) – 1-gigabit per second (Gbps) True-LVDS current mode logic (PCML), and HyperTransport – Clock-data synchronization (CDS) in True-LVDS interface to correct any fixed clock-to-data skew – ...

Page 2

... Programmable bus hold feature – Programmable pull-up resistor on I/O pins available during user mode EP2A25 EP2A40 2,750,000 3,000,000 900,000 1,500,000 24,320 38,400 152 160 622,592 655,360 36 ( 612 735 EP2A70 5,250,000 3,000,000 67,200 280 1,146,880 36 ( 1,060 Altera Corporation ...

Page 3

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet – Programmable output drive for 3.3-V LVTTL at 4 mA, 12 mA, 24 mA, or I/O standard levels – Programmable output slew-rate control reduces switching noise – Hot-socketing operation supported – Pull-up resistor on I/O pins before and during configuration Enhanced internal memory structure – ...

Page 4

... FineLine BGA 1.00 1.27 729 1,225 Notes 672-Pin 724-Pin BGA FineLine BGA 492 492 492 536 492 536 536 1,020-Pin FineLine BGA 1.00 1,089 33 33 (1), (2) 1,020-Pin FineLine BGA 735 Altera Corporation 1,508-Pin FineLine BGA 1.00 1,600 40 40 1,508-Pin FineLine BGA 1,060 ...

Page 5

... General Description Altera Corporation APEX II Programmable Logic Device Family Data Sheet APEX II devices integrate high-speed differential I/O support using the True-LVDS interface. The dedicated serializer, deserializer, and CDS circuitry in the True-LVDS interface support the LVDS, LVPECL, HyperTransport, and PCML I/O standards. Flexible-LVDS pins located in regular user I/O banks offer additional differential support, increasing the total device bandwidth ...

Page 6

... I/O standards into one device. Signal Description interconnections within APEX II devices (as well as to and from device pins) are provided by the FastTrack interconnect—a series of fast, continuous row and column channels that run the entire length and width of the device. 6 Altera Corporation ...

Page 7

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Each I/O pin is fed by an IOE located at the end of each row and column of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer and six registers that can be used for registering input, output, and output-enable signals ...

Page 8

... IOE Product Term Memory LUT Product Term IOE Memory IOE MegaLAB Columns Altera Corporation IOEs support PCI, GTL+, SSTL-3, LVDS, and other standards. Flexible integration of embedded memory, including CAM, RAM, ROM, FIFO, and other memory functions. ESBs 104 152 160 280 ...

Page 9

... LE8 LE9 LE10 Local Interconnect Altera Corporation APEX II Programmable Logic Device Family Data Sheet MegaLAB Structure APEX II devices are constructed from a series of MegaLAB Each MegaLAB structure contains a group of logic array blocks (LABs), one ESB, and a MegaLAB interconnect, which routes signals within the MegaLAB structure ...

Page 10

... LABs. If both the rising and falling edges of a clock are used in an LAB, both LAB-wide clock signals are used. 10 shows the APEX II LAB. The 10 LEs in the LAB are driven by two local interconnect areas. These LEs can drive two local interconnect areas. To/From Adjacent LAB, ESB, or IOEs Column Interconnect Altera Corporation ...

Page 11

... The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the LAB. (2) The SYNCCLR signal can be generated by the local interconnect or global signals. Altera Corporation APEX II Programmable Logic Device Family Data Sheet The LAB-wide control signals can be generated from the LAB local interconnect, global signals, and dedicated clock pins. The inherent low skew of the FastTrack interconnect enables used for clock distribution ...

Page 12

... LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In Cascade Synchronous Chain Load & Clear Logic Cascade-Out Register Bypass Packed Register Select Programmable Register To F astTrack Interconnect, PRN MegaLAB Interconnect Local Interconnect ENA CLRN To F astTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Altera Corporation ...

Page 13

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Each LE has two outputs that drive the local, MegaLAB, or FastTrack interconnect routing structure. Each output can be driven independently by the LUT’s or register’s output. For example, the LUT can drive one output while the register drives the other output. This feature, called register packing, improves device utilization because the register and the LUT can be used for unrelated functions ...

Page 14

... APEX II Programmable Logic Device Family Data Sheet Figure 6. APEX II Carry Chain 14 Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 Register s2 LE2 Register sn LEn Register Carry-Out LEn + 1 Altera Corporation ...

Page 15

... LUT d[7..4] LUT d[(4n — 1)..(4n — 4)] LUT Altera Corporation APEX II Programmable Logic Device Family Data Sheet Cascade Chain With the cascade chain, the APEX II architecture can implement functions with a very wide fan-in. Adjacent LUTs can compute portions of a function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via DeMorgan’ ...

Page 16

... LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. 16 Normal mode Arithmetic mode Counter mode Figure 8 shows the LE operating modes. Altera Corporation ...

Page 17

... The DATA1 and DATA2 input signals can supply counter enable down control, or register feedback signals for LEs other than the second LAB. (6) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in a LAB. Altera Corporation APEX II Programmable Logic Device Family Data Sheet LAB-Wide Clock Enable (2) ...

Page 18

... LAB. Consequently, if any of the LEs in an LAB use the counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. The Quartus II software automatically places any registers that are not used by the counter into other LABs. 18 Altera Corporation ...

Page 19

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet The counter mode uses two three-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used counter mode, the synchronous clear or load overrides any signal carried on the cascade chain ...

Page 20

... The row interconnect drives the MegaLAB interconnect to drive LEs, IOEs, or ESBs in a particular MegaLAB structure. 20 Figure 9. I/O MegaLAB MegaLAB MegaLAB MegaLAB MegaLAB MegaLAB I/O I/O I/O MegaLAB MegaLAB MegaLAB I/O I/O Altera Corporation I/O I/O I/O ...

Page 21

... B B MegaLAB Column Altera Corporation APEX II Programmable Logic Device Family Data Sheet A column line can be directly driven by the LEs, IOEs, or ESBs in that column. Row IOEs can drive a column line on a device’s left or right edge. The column line is used to route signals from one row to another. A column line can drive a row line ...

Page 22

... MegaLABs. Column pins using the FastRow interconnect achieve a faster set-up time, because the signal does not need to use a MegaLab interconnect line to reach the destination LE. the FastRow interconnect. 22 Row MegaLAB Interconnect Interconnect LE Local Interconnect TM lines for quickly routing input signals Column Interconnect Figure 12 shows Altera Corporation ...

Page 23

... Figure 12. APEX II FastRow Interconnect IOE FastRow Interconnect Altera Corporation APEX II Programmable Logic Device Family Data Sheet FastRow Interconnect IOE Drives Local Interconnect in Two MegaLAB Structures MegaLAB Select Vertical I/O Pins IOE IOE Drive Local Interconnect and FastRow Interconnect MegaLAB LABs Local ...

Page 24

... In product-term mode, each ESB contains 16 macrocells. Each macrocell consists of two product terms and a programmable register. shows the ESB in product-term mode. 24 summarizes how elements of the APEX II architecture drive each Destination LE ESB Local MegaLAB Interconnect Interconnect Row Column FastTrack FastTrack Interconnect Interconnect Altera Corporation FastRow Interconnect v Figure 13 ...

Page 25

... LAB Local Interconnect Note ot Figure 13: (1) PLL outputs cannot drive data input ports. Altera Corporation APEX II Programmable Logic Device Family Data Sheet 4 8 (1) Macrocells APEX II macrocells can be configured individually for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register ...

Page 26

... If both the rising and falling edges of a clock are used in an ESB, both ESB-wide clock signals are used. 26 ESB-Wide ESB-Wide Clears Clock Enables 2 Parallel Logic Expanders (From Other Macrocells) Product- Term Select Matrix ESB-Wide Clocks 2 2 Programmable Register D Q ENA Clock/ CLRN Enable Select Clear Select Altera Corporation ESB Output ...

Page 27

... Local Interconnect Local Interconnect Altera Corporation APEX II Programmable Logic Device Family Data Sheet The programmable register also supports an asynchronous clear function. Within the ESB, two asynchronous clears are generated from global signals and the local interconnect. Each macrocell can either choose between the two asynchronous clear signals or choose to not be cleared ...

Page 28

... Figure 17 28 From Previous Macrocell Product- Term Select Matrix Parallel Expander Switch Product- Term Select Matrix Parallel Expander Switch shows the ESB block diagram. Macrocell Product- Term Logic Macrocell Product- Term Logic To Next Macrocell Altera Corporation ...

Page 29

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Figure 17. Bidirectional Dual-Port Memory Configuration data [ ] A address A wren A clock A clocken aclr A In addition to bidirectional dual-port memory, the ESB also supports dual-port, and single-port RAM. Dual-port memory supports a simultaneous read and write. Single-port memory supports independent read and write ...

Page 30

... ESB in Table 6. Variable Width Configurations for Dual-Port RAM Read Port Width 1 bit 2 bits, 4 bits, 8 bits bits Write Port Width 2 bits, 4 bits, 8 bits bits 1 bit 16 in addition to Altera Corporation ...

Page 31

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet By combining multiple ESBs, the Quartus II software implements larger memory blocks automatically. For example, two 256 16 RAM blocks can be combined to form a 256 x 32 RAM block, and two 512 can be combined to form a 512 16 RAM block. Memory performance does not degrade for memory blocks up to 4,096 words deep. Each ESB can implement a 4,096-word-deep memory ...

Page 32

... APEX II Programmable Logic Device Family Data Sheet Figure 19. ESB in Input/Output Clock Mode Notes to Figure 19: (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. (2) This configuration is not supported for bidirectional dual-port configuration. 32 Note (1) Altera Corporation ...

Page 33

... Figure 20: (1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or chip-wide reset. Altera Corporation APEX II Programmable Logic Device Family Data Sheet In addition to the input/output mode clocking scheme, the clock connections to the various ESB input/output registers are customizable in ® ...

Page 34

... CAM supports writing “don’t care” bits into words of the memory. The don’t-care bit can be used as a mask for CAM comparisons; any bit set to don’t-care has no effect on matches. 34 Figure 21 shows the CAM block diagram. data[ ] wraddress[ ] wren inclock inclocken inaclr data_address[ ] match outclock outclocken outaclr Altera Corporation ...

Page 35

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet CAM can generate outputs in three different modes: single-match mode, multiple-match mode, and fast multiple-match mode. In each mode, the ESB outputs the matched data’s location as an encoded or unencoded address. When encoded, the ESB outputs an encoded address of the data’s location ...

Page 36

... ESB clock signals. Because the LEs drive the local interconnect, the LEs can control the WE and RE signals and the ESB clock, clock enable, and synchronous clear signals. shows the ESB control signal generation logic. 36 Application Note 119 (Implementing CAM). Figure 24 Altera Corporation ...

Page 37

... Local Interconnect Local Interconnect Local Interconnect Local Interconnect Altera Corporation APEX II Programmable Logic Device Family Data Sheet 8 4 RDEN WREN INCLOCK An ESB is fed by the local interconnect, which is driven by adjacent LEs (for high-speed connection to the ESB) or the MegaLAB interconnect. The ESB can drive the local, MegaLAB, or FastTrack interconnect routing structure to drive LEs and IOEs in the same MegaLAB structure or anywhere in the device ...

Page 38

... The output enable (OE) register can be used for fast clock-to- output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. 38 Figure 25 shows the structure of the APEX II IOE. The TM Altera Corporation ...

Page 39

... Figure 25. APEX II IOE Structure Logic Array OE Output Register Output A Output Register Output B Input A Input B Altera Corporation APEX II Programmable Logic Device Family Data Sheet OE Register Register CLK D Q The IOEs are located around the periphery of the APEX II device. Each IOE drives a row, column, MegaLAB, or local interconnect when used as an input or bidirectional pin. A row IOE can drive a local, MegaLAB, row, and column interconnect ...

Page 40

... An LE can drive a pin through the local interconnect for faster clock-to-output times. shows how a column IOE connects to the interconnect. MegaLAB Interconnect Each IOE can drive local, IOE MegaLAB, row, and column interconnect. Each IOE data and OE signal is driven by the local interconnect. IOE Altera Corporation ...

Page 41

... Any LE or ESB can drive a column pin through a row, column, and MegaLAB interconnect. Row Interconnect Altera Corporation APEX II Programmable Logic Device Family Data Sheet Each IOE can drive column and FastRow interconnects. Each IOE data and OE signal is driven by local interconnect. IOE ...

Page 42

... Output Enable 3 [OE3] Output Enable 4 [OE4] Output Enable 5 [OE5] Clock Enable 0 [CE0] Clock Enable 1 [CE1] Clock Enable 2 [CE2] Clock Enable 3 [CE3] Clock Enable 4 [CE4] Clock Enable 5 [CE5] I/O Control Signal CE, CLK CE, OE CE, CLK CE, OE CE, CLR CE, CLR Figure 28 shows the IOE in Altera Corporation ...

Page 43

... Figure 28. APEX II IOE in Bidirectional I/O Configuration Column, Row Eight or Local Dedicated Interconnect Clocks 12 Peripheral Signals Altera Corporation APEX II Programmable Logic Device Family Data Sheet OE Register D Q ENA CLRN/PRN Output Clock Enable Delay Chip-Wide Reset Output Register Logic Array to Output D Q Register Delay ...

Page 44

... Decrease input delay to internal cells Decrease input delay to input register Increase delay to output pin Increase delay to output enable pin Increase t delay to output pin ZX Increase output clock enable delay Increase input clock enable delay Decrease input delay to output register Altera Corporation Table 8 ...

Page 45

... Clocks 12 Peripheral Signals Chip-Wide Reset Altera Corporation APEX II Programmable Logic Device Family Data Sheet When using the IOE for DDR inputs, the two input registers are used to clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times ...

Page 46

... Register Delay ENA CLRN/PRN Output Register Logic Array to Output D Q ENA CLRN/PRN Output t Delay ZX VCCIO VCCIO OE Register t Delay CO Used for DDR SDRAM Output Propagation Delay clk Drive Strength Control Open-Drain Output Slew Control Altera Corporation Optional PCI Clamp Programmable Pull-Up Bus-Hold Circuit ...

Page 47

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Zero Bus Turnaround SRAM Interface Support In addition to DDR SDRAM support, APEX II device I/O pins also support interfacing with ZBT SRAM devices 200 MHz. ZBT SRAM blocks are designed to eliminate dead bus cycles when turning a bidirectional bus around between reads and writes, or writes and reads ...

Page 48

... Table 9. Programmable Drive Strength I/O Standard LVTTL (3.3 V) LVTTL (2.5 V) LVTTL (1.8 V) LVTTL (1.5 V) SSTL-3 class I and II SSTL-2 class I and II HSTL class I and II GTL+ (3.3 V) PCI PCI Current Strength OH OL Setting (default (default 8mA (default (default) Minimum (default) Altera Corporation ...

Page 49

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Bus Hold Each APEX II device I/O pin provides an optional bus-hold feature. When this feature is enabled for an I/O pin, the bus-hold circuitry weakly holds the signal at its last driven state. By holding the last driven state of the pin ...

Page 50

... Advanced I/O Standard Support APEX II device IOEs support the following I/O standards: 50 LVTTL LVCMOS 1.5-V 1.8-V 2.5-V 3.3-V PCI 3.3-V PCI-X 3.3-V AGP ( LVDS LVPECL PCML HyperTransport GTL+ HSTL class I and II SSTL-3 class I and II SSTL-2 class I and II CTT Differential HSTL Altera Corporation ...

Page 51

... Note to Table 10: (1) Differential HSTL is only supported on the eight dedicated global clock pins and four dedicated high-speed PLL clock pins. f Altera Corporation APEX II Programmable Logic Device Family Data Sheet Table 10 describes the I/O standards supported by APEX II devices. Type Voltage (V Single-ended Single-ended ...

Page 52

... I/O banks 5 and 6 support Flexible-LVDS and HyperTransport outputs and regular I/O pin standards. True-LVDS, LVPECL, PCML, and HyperTransport Input Block (2) (1) I/O Bank 3 I/O Bank 4 (1) True-LVDS, LVPECL, PCML, and HyperTransport Input Block (2) Devices). set to 3.3 V, 2.5 V, CCIO level to REF Altera Corporation ...

Page 53

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Each bank can support multiple standards with the same V and output pins. Each bank can support one voltage-referenced I/O standard, but it can support multiple I/O standards with the same V voltage level. For example, when V LVTTL, LVCMOS, 3 ...

Page 54

... These clock pins drive receiver PLLs only. They do not drive directly to the logic array. However, the receiver PLL can drive the logic array via a global clock line. 54 Notes (1), (2) + – Receiver Channel 1 + – Receiver Channel 2 + – Receiver Channel 18 J Bits Wide Deserializer Data to LEs To Global Clock Altera Corporation ...

Page 55

... Two sets of 18 transmitter channels are located in each APEX II device. Each set of 18 channels has one transmitter PLL. ( does not have to equal J. When the deserializer is bypassed. When DDR I/O registers are used. Altera Corporation APEX II Programmable Logic Device Family Data Sheet Notes (1), (2) W ...

Page 56

... N:1 topology (see topology matrix topology. Multi-bit CDS corrects for the skews inherent with these topologies, making them possible to use. 56 Table 11. Single-Bit CDS Training Patterns W/J Factor Table 11). Single-Bit CDS Pattern 0000011111 000001111 00001111 0000111 000111 00011 0011 Figure 34), a switch Altera Corporation ...

Page 57

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Figure 34. Multi-Bit CDS Supports N:1 Topology Clock Data APEX II Device Clock When using multi-bit CDS, the J and W factors do not need to be the same value. The byte boundary cannot be distinguished with multi-bit CDS ...

Page 58

... I/O output drivers (VCCIO). 58 Table 13 shows the Flexible-LVDS timing Speed Grade -7 -8 Min Max Min Max 400 311 700 900 1,100 1,400 Unit -9 Min Max 311 Mbps 900 ps 1,400 ps pins for CC Altera Corporation ...

Page 59

... Sequencing & Therefore, the V order. Hot Socketing Altera Corporation APEX II Programmable Logic Device Family Data Sheet level, input pins are 1.5-V, 1.8-V, 2.5-V and CCINT summarizes APEX II MultiVolt I/O support. Note (1) 2 ...

Page 60

... Figure 35. APEX II General-Purpose PLL inclock n f bin 60 Table 15. APEX II General-Purpose PLL Features Number of PLLs ClockBoost Feature 4 m/( Note (1) Phase Comparator Voltage-Controlled Oscillator Phase Shift Circuitry m Table 15 shows the Figure 35 shows an Number of External Number of Clock Outputs Feedback Inputs 8 clock0 k clock1 v Altera Corporation 2 ...

Page 61

... PLL input. m represents the multiplier. k and v represent the different post scale dividers for the two possible PLL outputs. m and k are integers that range from 1 to 160. n and v are integers that range from 1 to 16. Altera Corporation APEX II Programmable Logic Device Family Data Sheet Advanced ClockBoost Multiplication & Division ...

Page 62

... I/O pins. This feature is particularly important for advanced packages such as FineLine BGA packages because adding a connection to a pin during the debugging process can be difficult after a board is designed and manufactured must OUT OUT IN Altera Corporation ...

Page 63

... Bus hold and weak pull-up features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. Altera Corporation APEX II Programmable Logic Device Family Data Sheet All APEX II devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration ...

Page 64

... JTAG signals. Boundary-Scan Register Length 1,524 1,884 2,328 3,228 (1) Manufacturer 1 (1 Bit) Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 Altera Corporation ( ...

Page 65

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Figure 36. APEX II JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 19 shows the JTAG timing parameters and values for APEX II devices. ...

Page 66

... When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Device Output Device input rise and fall times < Test System C1 (includes jig capacitance) Altera Corporation ...

Page 67

... T Operating junction temperature J t Input rise time R t Input fall time F Altera Corporation APEX II Programmable Logic Device Family Data Sheet Tables 20 through 41 provide information on absolute maximum ratings, recommended operating conditions, and DC operating conditions for 1.5-V APEX II devices. Conditions With respect to ground ...

Page 68

... CCIO I = –0 3.0, CCIO Typical Maximum –10 10 – 150 Minimum Maximum 3.0 3.6 1.7 4.1 –0.5 0.8 –5 5 (10) 2.4 (10) 0.45 Minimum Maximum 3.0 3.6 1.7 4.1 –0.5 0.7 – – 0.2 CCIO 0.2 Altera Corporation Unit Units Units ...

Page 69

... Parameter V Output supply voltage CCIO V High-level input voltage Low-level input voltage IL I Input pin leakage current I V High-level output voltage OH V Low-level output voltage OL Altera Corporation APEX II Programmable Logic Device Family Data Sheet Note (10) Conditions CCIO I = –0 – –2 to – 0.1 mA ...

Page 70

... IN CCIO I = –500 A 0.9 OUT V CCIO I = 1,500 A OUT Conditions Minimum 1.35 0. 0.1 REF (10 Typical Maximum Units 3.3 3 CCIO 0.5 0 CCIO 0 CCIO Typical Maximum Units 3 CCIO 0.5 0. CCIO 0 CCIO 15 nH Typical Maximum Units 1.5 1.65 V 1.0 1. – 0.1 V REF 0.65 V Altera Corporation ...

Page 71

... Termination voltage TT V Reference voltage REF V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Altera Corporation APEX II Programmable Logic Device Family Data Sheet Conditions Minimum 2.375 V – 0.04 REF 1. 0.18 REF –0 –7 0.57 ...

Page 72

... V + 0.3 CCIO V – 0.2 REF V – 0.8 TT Typical Maximum 3.3 3.45 V 0.41 V CCIO CCIO V + 0.5 CCIO CCIO 0.3 V CCIO 3.6 CCIO 0.1 V CCIO 10 Typical Maximum 3.3 3. 0.5 CCIO CCIO 0.3 V CCIO 3.6 CCIO 0.1 V CCIO 10 Altera Corporation Units Units Units ...

Page 73

... Parameter V I/O supply voltage CCIO V (DC) DC input differential DIF voltage V (DC) DC common mode input CM voltage V (AC) AC differential input DIF voltage Altera Corporation APEX II Programmable Logic Device Family Data Sheet Conditions Minimum 1.4 0.68 0 0.1 REF –0 0.2 REF (10) V – 0.4 ...

Page 74

... Maximum 3.0 3.3 3.6 1.35 1.5 1.65 + 0.2 REF V REF – 0.4 REF V REF –10 10 Level 2.5 V 3.3 V Min Max Min 50 70 –50 –70 300 –300 and V CCINT . CCIO 48. Altera Corporation Units – 0 – 0 Units Max A A 500 A –500 A are CCIO ...

Page 75

... Altera Corporation APEX II Programmable Logic Device Family Data Sheet Figures 38 and 39 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 38. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform ...

Page 76

... Minimum Typical Maximum 3.135 3.3 3.465 V CCIO 0.3 V CCIO V – V CCIO CCIO 0.6 0 CCIO CCIO 0.3 V CCIO 300 450 600 85 325 85 325 100 Altera Corporation Units V ( Units V – – V – ...

Page 77

... Tables 42 – 45: (1) Maximum V is measured under static conditions. OD (2) When APEX II devices drive LVPECL signals, the APEX II LVPECL outputs must be terminated with a resistor network. Capacitance Altera Corporation APEX II Programmable Logic Device Family Data Sheet Note (2) Conditions Conditions R = 100 TT Table 46 and ...

Page 78

... See Figure 40. Figure 40. APEX II Maximum Input & Output Pin Capacitance I/O Bank I/O Bank 7 78 Conditions Minimum 1.0 MHz 1.0 MHz 1.0 MHz I/O Bank 1 I/O Bank 2 I/O Bank 6 I/O Bank Maximum Unit ( (1) pF I/O Bank I/O Bank 4 Altera Corporation ...

Page 79

... Timing Model Altera Corporation APEX II Programmable Logic Device Family Data Sheet The high-performance FastTrack and MegaLAB interconnect routing structures ensure predictable performance, and accurate simulation and timing analysis. In contrast, the unpredictable performance of FPGAs is caused by their segmented connection scheme. All specifications are always representative of worst-case supply voltage and junction temperature conditions ...

Page 80

... APEX II Programmable Logic Device Family Data Sheet Figure 41 Timing Model MAX LUT ESB t ESBARC t ESBSRC t ESBAWC t ESBSWC t ESBWASU t ESBWDSU t ESBSRASU t ESBWESU t ESBDATASU t ESBWADDRSU t ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD PTERMSU t PTERMCO Routing Delay t F1—4 t F5—20 t F20+ Altera Corporation ...

Page 81

... LE register hold time before clock register clock-to-output delay CO t LUT delay for data-in to data-out LUT Altera Corporation APEX II Programmable Logic Device Family Data Sheet Figure 42 shows the timing model for bi-directional, input, and output IOE timing. Figure 42. Synchronous External TIming Model Dedicated Clock ...

Page 82

... ESB clock-to-output delay without output registers ESBDATACO2 t ESB data-in to data-out delay for RAM mode ESBDD t ESB macrocell input to non-registered output PD t ESB macrocell register setup time before clock PTERMSU t ESB macrocell register clock-to-output delay PTERMCO Figure 82 Parameter shows the dual-port RAM timing microparameter waveform. Altera Corporation ...

Page 83

... Fan-out delay estimate using MegaLab interconnect; use to estimate routing delay for a F5-20 signal with fan-out Fan-out delay estimate using FastTrack interconnect; use to estimate routing delay for a F20+ signal with fan-out greater than 20 Altera Corporation APEX II Programmable Logic Device Family Data Sheet t ESBWEH ...

Page 84

... PLL clock-to-output buffer disable delay XZPLL t PLL clock-to-output buffer enable delay ZXPLL Note to Table 51: (1) External timing parameters are factory tested, worst-case values specified by Altera. These timing parameters are sample-tested only. 84 Parameter Note (1) Parameter Conditions Slow slew rate = OFF Slow slew rate = OFF Altera Corporation ...

Page 85

... ESBWADDRSU t 0.38 ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD 1.10 PTERMSU t PTERMCO Altera Corporation APEX II Programmable Logic Device Family Data Sheet Tables 52 through 67 show the APEX II device f parameters. -8 Speed Grade Max Min 0.29 0.29 0.18 0.53 -8 Speed Grade Max Min 1.28 2.49 2.20 3 ...

Page 86

... Max Min Max 0.29 0.29 0.18 0.20 0.53 0.61 -9 Speed Grade Unit Min Max 0.25 ns 0. Speed Grade Unit Min Max 1.32 ns 1.32 ns 0.17 ns 0.17 ns 1.32 ns 1.32 ns 1. Speed Grade Unit Min Max 0.33 ns 0.33 ns 0.23 ns 0.70 ns Altera Corporation ...

Page 87

... PTERMCO Table 58. EP2A25 f Routing Delays MAX Symbol -7 Speed Grade Min t 0.19 F1-4 t 0.65 F5-20 t 1.11 F20+ Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 1.28 1.47 2.49 2.86 2.20 2.53 3.02 3.47 0.07 0.18 0.43 ...

Page 88

... Speed Grade Max Min Max 0.26 0.26 0.16 0.18 0.48 0.55 -9 Speed Grade Unit Min Max 2.12 ns 2.12 ns 0.17 ns 0.17 ns 2.12 ns 2.12 ns 1. Speed Grade Unit Min Max 0.29 ns 0.29 ns 0.21 ns 0.63 ns Altera Corporation ...

Page 89

... PTERMCO Table 62. EP2A40 f Routing Delays MAX Symbol -7 Speed Grade Min t 0.17 F1-4 t 1.12 F5-20 t 1.49 F20+ Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 2.28 2.62 2.23 2.56 3.13 3.60 2.76 3.18 1.37 0.00 1.66 ...

Page 90

... Speed Grade Max Min Max 0.34 0.34 0.22 0.25 0.66 0.76 -9 Speed Grade Unit Min Max 1.88 ns 1.88 ns 0.16 ns 0.16 ns 1.88 ns 1.88 ns 1. Speed Grade Unit Min Max 0.39 ns 0.39 ns 0.29 ns 0.87 ns Altera Corporation ...

Page 91

... PTERMCO Table 66. EP2A70 f Routing Delays MAX Symbol -7 Speed Grade Min t 0.15 F1-4 t 1.21 F5-20 t 1.87 F20+ Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 3.12 3.58 3.11 3.58 4.41 5.07 3.82 4.39 1.99 0.00 2.15 ...

Page 92

... Speed Grade Max Min Max 2.53 2.53 0.21 0.21 2.53 2.53 1.79 1.50 -9 Speed Grade Min Max 2.46 0.00 2.00 4.90 6.26 6.26 1.42 0.00 0.50 3.16 4.52 4.52 Altera Corporation Unit Unit ...

Page 93

... INH t 2.00 OUTCO 1.17 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL t XZPLL t ZXPLL Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 2.34 0.00 4.36 2.00 4.75 5.57 6.24 5.57 6.24 1.37 0.00 2.90 0.50 3.16 4.12 4.65 4 ...

Page 94

... Speed Grade Unit Min Max 2.64 ns 0.00 ns 2.00 5.24 ns 7.01 ns 7.01 ns 1.47 ns 0.00 ns 0.50 3.33 ns 5. Speed Grade Unit Min Max 1.88 ns 0.00 ns 2.00 5.61 ns 7.53 ns 7.53 ns 1.38 ns 0.00 ns 0.50 3.06 ns 4.97 ns 4.97 ns Altera Corporation ...

Page 95

... INH t 2.00 OUTCO 1.19 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL t XZPLL t ZXPLL Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 2.16 0.00 4.96 2.00 5.29 7.04 7.59 7.04 7.59 1.31 0.00 2.66 0.50 2.87 4.74 5.17 4 ...

Page 96

... Speed Grade Max Min Max 2.99 0.00 4.91 2.00 5.24 6.16 6.71 6.16 6.71 1.30 0.00 2.67 0.50 2.86 3.92 4.34 3.92 4.34 -9 Speed Grade Unit Min Max 3.22 ns 0.00 ns 2.00 5.60 ns 7.32 ns 7.32 ns 1.43 ns 0.00 ns 0.50 3.08 ns 4.79 ns 4.79 ns Altera Corporation ...

Page 97

... SSTL-2 Class I SSTL-2 Class II HSTL Class I HSTL Class II LVDS LVPECL PCML CTT 3.3-V AGP 1 3.3-V AGP 2 HyperTransport Differential HSTL Altera Corporation APEX II Programmable Logic Device Family Data Sheet -8 Speed Grade Max Min Max 0.00 0.00 0.00 0.00 0.10 0.11 0.00 0.00 ...

Page 98

... Speed Grade Unit Min Max 0.00 ns 0.00 ns 4.20 ns 3.36 ns 1.52 ns 0.85 ns 0.85 ns 0.57 ns 0.66 ns 0.66 ns 0.86 ns 1.02 ns 0.10 ns 0.30 ns 1.79 ns 1.74 ns 1.65 ns 0.00 ns 0.00 ns 0.00 ns 1.55 ns 1.79 ns Altera Corporation ...

Page 99

... Figure 43. Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...

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