RTL8208 REALTEK, RTL8208 Datasheet
RTL8208
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RTL8208 Summary of contents
Page 1
... Clock Circuit ........................................................ 32 8.4 2.5V power........................................................... 32 8.5 Power Planes ........................................................ 32 8.6 Ground Planes ...................................................... 32 8.7 Transformer Options ............................................ 32 9.1 10Base-T/100Base-TX Application ..................... 33 9.2 100Base-FX Application...................................... 34 10.1 Absolute Maximum Ratings............................... 35 10.2 Operating Range ................................................ 35 10.3 DC Characteristics ............................................. 35 10.4 AC Characteristics.............................................. 36 10.5 Digital Timing Characteristics ........................... 37 10.6 Thermal Data...................................................... 38 RTL8208 Rev.1.97 ...
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... Realtek patent to obtain fewer pin-count. Flexible hardware settings are provided to configure the various operating modes of the chip. The RTL8208 consists of 8 separate and independent channels. Each channel consists of an RMII/SMII/SS-SMII interface to MAC controller, and hardware pins are used to configure the interface for RMII, or SMII, or SS-SMII mode ...
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... SMII TX TXD0 RMII TXD1 TXE TX N 2003/04/04 RXCL K RXD[3:0 4B/5 ] DECOD STAT X RXD E MACHIN V E BYP-DESC R RX RECEIVER CO T TXCL L STAT X FX enable TXE K MACHIN E TXE BYP-SC R TXD[3:0 MLT ENCODE ] TX TRANSMITTER 3 FX input TP input 10/100 3 TX/FX DRIVE R R RTL8208 RX+/- TX+/- Rev.1.97 ...
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... IBREF 119 VDDAL 120 RXIN[0] 121 RXIP[0] 122 VSSA 123 TXOP[0] TXON[0] 124 125 VDDAH 126 VDDAH 127 TXON[1] 128 TXOP[1] 2003/04/04 RTL8208 08042T1 050A TAIWAN 4 RTL8208 64 TX_EN[6] 63 TXD0[6] 62 TXD1[6] 61 CRS_DV[6] 60 RXD0[6] 59 RXD1[6] 58 VSS 57 VDD 56 TX_EN[7] 55 TXD0[7] 54 TXD1[7] 53 CRS_DV[7] 52 RXD0[7] ...
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... TXD0[0] AVDD TX_EN[0] I VSS I/O MDIO I/O MDC I/O X1 I/O X2 I/O VCTRL I/O VDDAH I IBREF I VDDAL I RXIN[0] DVDD RXIP[0] DGND VSSA I/O TXOP[0] I/O TXON[0] I/O VDDAH I VDDAH I TXON[1] I TXOP[1] 5 RTL8208 Pin# Type DVDD 72 DGND 73 I DVDD I/O 82 DGND 83 I/O ...
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... AO Transmitter Output: Differential negative signal shared by 100Base-TX, 100Base-FX, 10Base-T. Type Description P Power for IBREF P 3.3V Power to analog: Used for transmitters and equalizers. P 2.5V Power to analog: Used for PLL circuits. G Analog ground P Digital 2.5V power supply G Digital ground 6 RTL8208 Rev.1.97 ...
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... SMII/SS-SMII mode. A Reference Bias Resistor: This pin must be tied to analog ground through an external 1.96KΩ resistor when using a 1:1 transformer on Tx/Rx. O Voltage control: This pin controls a PNP transistor to generate the 2.5V power supply for VDD and VDDAL pins. 7 RTL8208 Rev.1.97 ...
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... Sync/Transmit Synchronous: In SMII, SYNC is a sync signal used to delimit a 10-bit segment of RXD0 and TXD0 for all ports. In SS-SMII, TX_SYNC is a sync signal used to delimit the 10-bit segment of TXD0 for all ports. I Transmit Clock/Transmit Enable: In SS-SMII, TX_EN[4] of RMII is used as TX_CLK, which is a 125MHz clock input from MAC. 8 RTL8208 Rev.1.97 ...
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... Management Data I/O. Bi-directional data interface. A 1.5KΩ (Pu) pull-up resistor is required (as specified in IEEE802.3u). The MAC controller access of the MII registers should be delayed at least 700us after completion of the reset because of the internal reset operation of the RTL8208 I, Management Data Clock 25MHz clock sourced by MAC to (Pd) sample MDIO. ...
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... LEDMODE[1:0]: (default = 00) Controls the forms of serial LED status. (Pd,Pd) LEDMODE Mode 2’b00 3-bit serial stream 2’b01 2-bit serial stream 2’b10 3-bit for Bi-color LED Col/Fulldup, Link/Act, Spd See LED operation mode section for more information. 10 RTL8208 Output Col/Fulldup, Link/Act, Spd Spd, Link/Act Rev.1.97 ...
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... Type Description I/O, Reserved for internal use. Must be kept floating. (Pd) I/O, TEST. Reserved for internal use. Must be kept floating. (Pd) I/O, Reserved for internal use. Must be kept floating. (Pd) 11 the output driving abilities RTL8208 of the Rev.1.97 ...
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... When Nway is enabled, this bit reflects the result of Auto-negotiation. (Read only) When Nway is disabled, this bit can be set by SMI*. (Read/Write) When 100FX is enabled, this bit is determined by the FX_DUPLEX pin. (Read/Write) 1=Full duplex operation. 0=Half duplex operation. 12 RTL8208 Default 3100 0F49 001C C883 05E1 0001 0000 ...
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... Reset – In order to reset the RTL8208 by software control, a ‘1’ must be written to bit 15 using an SMI write operation. The bit clears itself after the reset process is complete, and does not need to be cleared using a second SMI write. Writes to other Control register bits will have no effect until the reset process is completed, which requires approximately 1us. Writing a ‘0’ to this bit has no effect. Because this bit is self clearing after a few cycles from a write operation, it will return a ‘ ...
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... Auto-negotiation function has been disabled. Link Status – The RTL8208 will return a ‘1’ on bit 2 when the link state machine is in Link Pass, indicating that a valid link has been established. Otherwise, it will return ‘0’. When a link failure occurs after the link pass state has been entered, the Link ...
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... Jabber Detect – The RTL8208 will return a ‘1’ on bit jabber condition has been detected. After the bit is read the chip is reset, it reverts to ‘0’. This is for 10Base-T only. Jabber occurs when a predefined excessive long packet is detected for 10Base-T ...
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... Selector Field Next Page – The RTL8208 does not implement the Next Page function, so bit 15 will always return a ‘0’ when read. Acknowledge – Because the Next Page function is not implemented, bit 14 will always return a ‘0’ when read. Remote Fault – When RTL8208 can not receive valid signal , set Reg4.13=1. The RTL8208 advertises this information to inform link partner. Reserved – ...
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... Acknowledge – Bit 14 is used by Auto-negotiation to indicate that a device has successfully received its Link Partner’s Link Code Word. Remote Fault – Bit 13 returns a value of ‘1’ when the Link Partner signals that it has detected a remote fault. The RTL8208 advertises this information, but does not act upon it. ...
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... Link Partner Ability Register. Local Next Page Able – The RTL8208 does not have Next Page capabilities will always return a ‘0’ when bit 2 is read. Page Received – Bit 1 is latched high when a new link code word is received from the Link Partner, checked and acknowledged. ...
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... Port Pair Loop Back Mode (PP-LPBK) PP-LPBK mode is enabled by pulling pin 81 high on reset. When in PP-LPBK mode, the ports of the RTL8208 is configured as four pairs, port0 & port1, port2 & port3, port4 & port5, and port 6 & port7. Each pair are set as RMII interface loop back, acting like a signal regeneration /transformation repeater switch controller is not necessary ...
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... Initialization and Setup 7.2.1 Reset The RTL8208 is initialized while in a reset state. During reset, each transceiver will be reset simultaneously. There are 3 ways to reset the RTL8208: Power-on auto reset; hardware pin reset; and software reset. The internal power-on auto reset circuit can reset the chip while the reset pin (pin47) is floating ...
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... Transmit Function Upon detection of TX_EN high, the RTL8208 converts RMII/SMII/SS-SMII TXD to 5 bit code-group and substitutes J/K code-groups for the first 2 code-groups, which are called Start of Stream Delimiter (SSD). 4B5B coding continues for all of the data as long as TX_EN is asserted high ...
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... Transmit Error (used to force signaling errors) 00000 Invalid code 00001 Invalid code 00010 Invalid code 00011 Invalid code 00101 Invalid code 00110 Invalid code 01000 Invalid code 01100 Invalid code 10000 Invalid code 11001 Invalid code 4B5B Encoding 22 Definition RTL8208 Rev.1.97 ...
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... PHY. Any of the RTL8208 transceivers may interface with an external 100Base-FX fiber optic device and receiver instead of the magnetics module used with twisted pair cable. The differential transmit and receive data pairs will operate at PECL voltage levels instead of those required for twisted-pair transmission ...
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... On the other hand, if the RTL8208 detects no valid link pulse on RxOP/N pair, it sends out a FEFI stream pattern, which in turn will cause the remote side to detect a Far-End-Fault indication. This means the RTL8208 sees problems on the receive path. ...
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... RMII Signal Diagram 50MHz Oscillator Solution 7.6.2 SMII (Serial MII) The RTL8208 also supports SMII interface to MAC, which allows a further reduction in the number of signals. As illustrated below, both the MAC and RTL8208 are synchronous to a 125MHz reference clock. 2003/04/04 8-port RTL8208 ...
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... REFCLK SYNC SYNC SYNC TX_ER TX_ER TX_ER TX_EN TX_EN TX_EN Collision Detection The RTL8208 does not indicate that a collision has occurred left up to the MAC to detect the assertion of both CRS_DV and TX_EN. 2003/04/04 RXD2 RXD1 RXD3 Speed Duplex Link 0 =10Mbps 0 = Half ...
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... MII receive path. The PHY can sample one of the ten segments TX_CLK TX_SYNC TXD[0] TX_ER TX_EN Collision Detection The RTL8208 does not indicate that a collision has occurred left up to the MAC to detect the assertion of both CRS_DV and TX_EN. 2003/04/04 TX_SYNC TXD0[7:0] TX_CLK 8-port RX_SYNC MAC ...
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... Power Saving and Power Down Mode 7.7.1 Power Saving Mode The RTL8208 implements a power saving mode on a per port basis. One port automatically enters power saving mode 10 seconds after the cable is disconnected from it, regardless of whether the RTL8208’s operation mode is Nway or Force mode. ...
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... Col/Dup LED port 3 Spd LED port 3 Link/Act LED port 3 Col/Dup LED port 2 Spd LED port 2 Link/Act LED port 2 Col/Dup LED port 1 Spd LED port 1 Link/Act LED port 1 Col/Dup LED port 0 Spd LED port 0 Link/Act LED port 0 Col/Dup LED RTL8208 2. Spd Rev.1.97 ...
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... During the link setup phase, the RTL8208 checks for reception of active signals on every port to determine if a connection can be established. If the receive data pin pair is connected to receive pin pair of the peer device (and vice versa), the RTL8208 will automatically change its configuration to swap receive data pins with transmit data pins. In other words, the RTL8208 can adapt automatically to a peer device's configuration ...
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... Power Generation The RTL8208 uses a PNP transistor to generate 2.5V from the 3.3V power supply. This 2.5V provides for digital core and analog receive circuits. Once your system needs more than one RTL8208 chip (greater than 8 ports), do not use one PNP transistor for all of the RTL8208 chips even if the rating is enough ...
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... Clock Circuit • The clock should be 25M/50MHz/125MHz 100ppm with jitter less than 0.5ns. • If use 50MHz or 125MHz as clock source, make the length of clock path to RTL8208 equal to the length to MAC as possible. The length difference should under 1 inch. • If use 50MHz, please put a damping resistor at clock source side. ...
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... The Central Tap in the primary side of H1164 must be left floating, and cannot be bypassed to GND via capacitor. 2003/04/04 Pulse H1164 50Ω 1:1 1% 50Ω 0.1uF 1% 50Ω 1:1 1% 50Ω 0.1uF 1% 1.96ΚΩ, 1% 10Base-T/100Base-TX Diagram 33 RTL8208 RJ45 75Ω ∗ 3 0.1uF/3KV Chasis GND Rev.1.97 ...
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... Application (3.3V Fiber Transceiver) 34 VCC_RX (3.3V) DELTA 82Ω 82Ω OPT-155A2H1 1*9 SC Duplex FDDI Fast Ethernet Optical 130Ω Transceiver Module 1 GND_RX 2 RD+ RD VCC_RX (3.3V) 5 VCC_RX VCC_TX (3.3V) 6 VCC_TX 7 TD- 8 TD+ 9 GND_TX Chasis GND RTL8208 Rev.1.97 ...
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... Power down 35 Maximum Units °C +150 +4.0 V VDD V VDD V Maximum Units °C +50 3.45 V 2.625 V Min Typical 81.2 88.9 125.5 145.7 76.7 15.5 88.5 499.2 370.7 371.3 48.1 3.3 495 1870 1537 1590 350 50 1.5 -10 3 2.25 0 RTL8208 Max Units 1 2.75 V 0.25 V Rev.1.97 ...
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... Return loss from 5MHz to 10MHz for reference resistance of 100 Ω. Terminate each end with 50Ω resistive load. Return loss from 5MHz to 10MHz for reference resistance of 100Ω. dB below fundamental, 20 cycles of all ones data TP_IDL width 36 RTL8208 Min Typical Max Units ...
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... SMII Timing TXD, SYNC to REFCLK rising edge setup time TXD SYNC to REFCLK rising edge hold time Output delay from REFCLK rising edge to RXD SMI Timing MDC clock rate Write cycle Write cycle Read cycle 37 RTL8208 Min Typical Max Units 11 12 Bits 15 16 ...
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... Thermal resistance: junction to case * PCB conditions (JEDEC JESD51-7) : dimensions : 76.2 x 114.3 mm, thickness : 1.6mm 2003/04/ Cross-section of 128 PQFP Conditions Conditions 2 layer PCB, 0 ft/s airflow 2 layer PCB, 0 ft/s airflow 38 RTL8208 Min Typical Max Units ° 125 °C Min Typical Max Units 30.1 ° ...
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... TITLE : 128 QFP (14x20 mm ) PACKAGE OUTLINE 0.25 0.5 0.75 APPROVE 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0° - 12° REALTEK SEMI-CONDUCTOR CO., LTD 39 -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL : DOC. NO. 530-ASS-P004 VERSION PAGE DWG NO. Q128 - 1 DATE Oct. 08 1998 RTL8208 1 OF Rev.1.97 ...
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... Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 WWW: www.realtek.com.tw 2003/04/04 40 RTL8208 Rev.1.97 ...