RTL8801 REALTEK, RTL8801 Datasheet

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RTL8801

Manufacturer Part Number
RTL8801
Description
IEEE 1394A 100/200/400 Mbits/s 3 Port Cable Transceiver/Arbiter (PHY) Chip
Manufacturer
REALTEK
Datasheet

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RTL8801 PHY/IEEE 1394a
1. Features
2. General Description
The RTL8801 provides three-port physical layer(PHY) function in a cable-based IEEE 1394-1995
and IEEE P1394a network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and transmission.
Data bits to be transmitted through the cable ports are received from the Link on 2/4/8 data lines
(D0-D8), and are latched internally in the RTL8801 in synchronization with the 49.152 MHZ
system clock these bits are combined serially, encoded, and transmitted at 98.304 , 196.608 or
393.216Mbps as the outbound data-strobe information stream. During transmission, the encoded
2002,7,1
Fully support provisions of IEEE1394-1995
Provides three fully compliant cables ports
Fully
Full P1394a additional function support
Support optional 1394 Annex J electrical
Cable power presence monitoring
Separate cable bias (TPBIAS) and driver
for High- Performance Serial Bus and the
P1394a draft 2.0 standard
at 100/200/400 Mbits/s and available with
three ports
requirements
isolation barrier at PHY-link interface
Support power-down feature to conserve
energy in battery–powered applications
termination voltage supply for each port
3 port 100/200/400 Mb/s Cable Transceiver/Arbiter Chip
compliant
with
Open
HCI
Encode and decode functions included for
Support LPS/link-on pin for PHY-link
Incoming data resynchronized to local
Single
Node power-class information signaling for
Adaptive equalizer
Easy configured as a repeater
Single 3.3V power supply
64 pin LQFP package
data-strobe bit level encoding
interface
clock
transmit/receive
Mbits/s and LLC clock at 49.152 MHZ
system power management
24.576
MHZ
data
RTL8801-Ver. K
at
crystal
Datasheet
100/200/400
provide
1

Related parts for RTL8801

RTL8801 Summary of contents

Page 1

... Data bits to be transmitted through the cable ports are received from the Link on 2/4/8 data lines (D0-D8), and are latched internally in the RTL8801 in synchronization with the 49.152 MHZ system clock these bits are combined serially, encoded, and transmitted at 98.304 , 196.608 or 393 ...

Page 2

... The presence or absence of this common-mode voltage is used as an indication of cable connection status. The cable connection status signal is internally debounced in the RTL8801 on a cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset cable disconnect-to-connect a debounce delay is incorporated ...

Page 3

... Pin Assignment LREQ DVSS CTL0 CTL1 D0 D1 DVDD DVSS LACT LPS 2002,7,1 RTL8801 RTL8801-Ver. K Datasheet TPBIAS3 TPA3+ TPA3- TPB3+ TPB3- PVDD TPBIAS2 TPA2+ TPA2- TPB2+ TPB2- TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- 3 ...

Page 4

... Power class indicator. The PC signals set the bit values of the three power class bits in Self-ID packet . These bits can be programed by RTL8801-Ver. K Datasheet Description 4 ...

Page 5

... Reset. An external capacitor is required for proper power-up operation. 28 Test control pin. This pin is used in the manufacturing test of the device. For normal use it should be tied to DVSS. 27 Test control pin. This pin is used in the manufacturing test of the device. For normal use it should be tied to DVDD. RTL8801-Ver. K Datasheet 5 ...

Page 6

... Current Generator Cable Port 1 Arbitration and Control State Machine Logic Cable Port 2 Cable Port 3 Crystal Transmit Oscillator, Data PLL System, Encoder and Clock Generator RTL8801-Ver. K Datasheet TPBIAS1 TPBIAS2 TPBIAS3 TPA1+ TPA1- TPB1+ TPB1- TPA2+ TPA2- TPB2+ TPB2- TPA3+ TPA3- TPB3+ TPB3- XI ...

Page 7

... PHY chip. The width of the data bus scales with the highest speed both chips can support, using two pins per 100 Mbit/s. The clock rate of the signals at this interface remains constant, independent of speed, to support galvanic isolation for implementations where it is 2002,7,1 RTL8801-Ver. K Datasheet 7 ...

Page 8

... Extended(7) 0011b Max_speed 0100b Link_ac Contend tive er 0101b Resume ISBR Loop _int 0110b 0111b Page_select 1000b 1111b 2002,7 Physical_ID Gap_count reserved Total_ports reserved Jitter Pwr_fail Timeout Port_ev ent Reserved reserve Port_select Register0(page_select) Register7(page_select) RTL8801-Ver. K Datasheet Delay Pwr_class Enab_ac Enab_m cel ulti 8 ...

Page 9

... Otherwise cleared or set by software to control the value of the L bit transmitted in the self-ID packet. The transmitted L bit shall be the logical AND of this bit and the LPS signal. Contender. Cleared or set by software to control the value of the C bit transmitted in the self-ID packet. RTL8801-Ver. K Datasheet 9 ...

Page 10

... Arbitration state machine timeout. A write of one to this bit clears it to zero. Port event detect. The PHY sets this bit to one if any of connected, Bias, Disabled or Fault change for a port whose Int_enable bit is one. The PHY also sets this bit to one if resume RTL8801-Ver. K Datasheet 10 ...

Page 11

... PHY register address 1000b through 1111b, inclusive. information, this field selects which port’s registers are accessible through the window at PHY register addressed 1000b through 1111b, inclusive BStat Child connected Int_enable Fault RTL8801-Ver. K Datasheet 6 7 Bias Disabled 11 ...

Page 12

... Mbit/s 010 – 98.304, 196.608 and 393.216 Mbit/s Enable port event interrupts. When set to one, the PHY shall set Port_event to one if any of Connected, Bias, Disabled or Fault (for this port) change state. Set to one if an error is detected during a suspend or RTL8801-Ver. K Datasheet 12 ...

Page 13

... Vendor_ID. The most significant byte of Product_ID appears at PHY register location 1101 and the least significant at 1111. The default value is “88 01 00”. 2002,7,1 resume operation. A write of one to this bit clears it to zero Compliance_level Reserved Vendor_ID Product_ID RTL8801-Ver. K Datasheet ...

Page 14

... LLC LLC LLC LLC LLC DVSS LACT Link act LPS LLC or VDD 2002,7 4.7k ohm 0.1uF RTL8801 68k ohm RTL8801-Ver. K Datasheet TPBIAS TPBIAS3 3 TPA3+ TPA3- TP cable 3 TPB3+ TPB3- PVDD VDD TPBIAS2 TPBIAS2 TPA2+ TPA2- TP cable TPB2+ 2 TPB2- TPBIAS TPBIAS1 1 TPA1+ TPA1- ...

Page 15

... Dn, CTLn, LREQ Input Setup and Hold Timing Waveforms SYSCLK Tsu Dn, CTLn, LREQ Symbol Parameter Tsu Setup time, Dn, CTLn, LREQ to Sysclk Th Hold time, Dn, CTLn, LREQ before Sysclk 2002,7,1 Min. Type. -0.3V -65 ¢ J Min. Type. 3.0V 0 ¢ Min Type. Max RTL8801-Ver. K Datasheet Max. 4V 150 ¢ J Max. 3.6 70 ¢ J Units ...

Page 16

... Reference document : JEDEC MS-026 , BBC TITLE : 64LD LQFP ( 10x10x1.4mm) PACKAGE OUTLINE DRAWING , FOOTPRINT 2.0mm RTL8801-Ver. K Datasheet do not include mold 1 are maximum plastic body 1 16 ...

Page 17

... This document has been carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd. assumes no responsibility for inaccuracies. 2002,7,1 LEADFRAME MATERIAL: APPROVE 3 CHECK REALTEK SEMI-CONDUCTOR CO., LTD RTL8801-Ver. K Datasheet DOC. NO. VERSION 1 PAGE OF DWG NO. LQ064 - P1 DATE NOV. 06.1997 17 ...

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