HDMP-1646A Agilent Technologies, Inc., HDMP-1646A Datasheet
HDMP-1646A
Specifications of HDMP-1646A
Available stocks
Related parts for HDMP-1646A
HDMP-1646A Summary of contents
Page 1
... Transmitter and Receiver Functions Incorporated onto a Single IC • Three Package Sizes Available: – TQFP (HDMP-T1636A) – PQFP (HDMP-1636A) – PQFP (HDMP-1646A) • 10-Bit Wide Parallel TTL Compatible I/Os • Single +3.3 V Power Supply • 5-Volt Tolerant I/Os • ESD Protection on All Pins Applications • ...
Page 2
... PROTOCOL DEVICE RBC0 RBC1 BYTSYNC REFCLK ENBYTSYNC Figure 1. Typical Application Using the HDMP-1636A/1646A/T1636A. DATA BYTE FRAME TX[0-9] MUX TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR REFCLK RXCAP0 RXCAP1 RBC0 RBC1 FRAME DATA BYTE DEMUX RX[0-9] AND BYTE SYNC BYTSYNC ENBYTSYNC Figure 2. HDMP-1636A/1646A/T1636A Transceiver Block Diagram. ...
Page 3
... T1636A was designed to transmit and receive 10-bit wide parallel data over a single high-speed line. The parallel data applied to the transmitter is expected to be 8B/10B encoded. In order to accomplish this task, the HDMP- 1636A/1646A/T1636A incorporates the following: • TTL Parallel I/Os • High Speed Phase Locked Loops • ...
Page 4
... SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (or a K28.5 character) of positive disparity (0011111xxx). When recognized, HDMP-1636A/1646A/T1636A (Transmitter Section) – Gigabit Ethernet Timing Characteristics + 3. 3. Symbol ...
Page 5
... HDMP-1636/1646A/T1636A (Transmitter Section) – Fibre Channel Timing Characteristics Symbol Parameter t Setup Time setup t Hold Time hold [2] t_txlat Transmitter Latency Notes: 1. Device tested and characterized under T 2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit transmitted) ...
Page 6
... The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0). HDMP-1636/1646A/T1636A (Receiver Section) – Fibre Channel Timing Characteristics A [1] ...
Page 7
RBC1 RX[0]-RX[9] K28.5 BYTSYNC RBC0 Figure 5. Receiver Section Timing. DATA BYTE C ± DIN RX[0]-RX[9] RBC1/0 Figure 6. Receiver Latency. DATA DATA DATA DATA BYTE ...
Page 8
... Max. 124.0 126.0 Guaranteed Operating Rates – Fibre Channel + 3. 3. Parallel Clock Rate (MHz) Min. Max. 106.20 106.30 HDMP-1636A/1646A/T1636A (TRx) Transceiver Reference Clock Requirements + 3. 3. Symbol Parameter f Nominal Frequency (for Gigabit Ethernet Compliance) f Nominal Frequency (for Fibre Channel Compliance) F Frequency Tolerance ...
Page 9
... HDMP-1636A/1646A/T1636A (TRx) DC Electrical Specifications + 3. 3. Symbol V TTL Input High Voltage Level, Guaranteed High Signal IH,TTL for All Inputs V TTL Input Low Voltage Level, Guaranteed Low Signal for IL,TTL All Inputs V TTL Output High Voltage Level, I OH,TTL V TTL Output Low Voltage Level, I ...
Page 10
... Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-. a. Differential HS_OUT Output (Dout+ Minus Dout-). b. Single-Ended HS_OUT Output (Dout+). Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1636A/1646A/T1636A as Captured on the 83480A Digital Communications Analyzer. Tested with PRBS = 2 Figure 7. Transmitter DOUT Eye Diagrams. ...
Page 11
... Specified with high speed outputs biased with 150 4. Based on independent package testing by Agilent Technologies. Watt for the HDMP-T1636A / HDMP-1646A. the actual junction temperature in a given application, use the following: T measured on the top center of the package and P Parameter ...
Page 12
... I-TTL Input TTL, Floats High When Left Open O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground HDMP-1636A/46A/T1636A (TRx) Pin Input Capacitance Symbol C Input Capacitance on TTL Input Pins INPUT O_TTL V _RXTTL ...
Page 13
... TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. *GND: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY. HOWEVER RECOMMENDED THAT THIS PIN BE CONNECTED TO GND IN ORDER TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT. Figure 11. HDMP-1636A/1646A/T1636A (TRx) Package Layout and Marking, Top View ...
Page 14
TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of a comma character (0011111XXX only active when ENBYTSYNC is enabled. -DIN 52 HS_IN Serial Data Inputs: High-speed ...
Page 15
TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL RX[1] 44 RX[2] 43 RX[3] 41 RX[4] 40 RX[5] 39 RX[6] 38 RX[7] 36 RX[8] 35 RX[9] 34 RXCAP0 48 C RXCAP1 49 SIG_DET 26 O-TTL TX[0] 2 I-TTL TX[1] ...
Page 16
... The PLL capacitors are placed physically close to the appropriate pins on the HDMP-1636A/1646A/ T1636A. Keeping the lines short will prevent them from picking up stray noise from surrounding lines or components. ...
Page 17
... BASIC + 0.15/ ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER D1/E1 HDMP-T1636A TOLERANCE ± 0.20 ± 0.20 ± 0.05 Figure 13. Mechanical Dimensions of HDMP-1636A/1646A/T1636A. Details Plastic 85% Tin, 15% Lead 300-800 m HDMP-1636A 0.08 mm max HDMP-T1636A 0.08 mm max HDMP-1646A 0.10 mm max ...
Page 18
... Data subject to change. Copyright © 2000 Agilent Technologies, Inc. Obsoletes 5967-6245E 5968-3339E (4/00) ...