CY7C1372BV25 Cypress Semiconductor Corporation., CY7C1372BV25 Datasheet
CY7C1372BV25
Related parts for CY7C1372BV25
CY7C1372BV25 Summary of contents
Page 1
... Write cycle is initiated. The CY7C1370BV25 and CY7C1372BV25 have an on-chip two-bit burst counter. In the burst mode, the CY7C1370BV25 and CY7C1372BV25 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence ...
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... DQb 23 58 DQa DPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DPa CY7C1372BV25 CY7C1370BV25 150 MHz 133 MHz Unit 3.8 4.2 190 160 CY7C1372BV25 66 (1M × 18 Page DDQ DPa DQa DQa DDQ DQa DQa DQa DQa V DDQ V SS DQa DQa DDQ NC ...
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... BWS CLK BWS CEN MODE V DD 64M A A TMS TDI TCK CY7C1372BV25 (1M × 18)–7 × 17 BGA ADV/ BWS CLK CEN MODE 32M TMS TDI TCK CY7C1372BV25 CY7C1370BV25 DDQ DDQ BWS DDQ BWS DDQ 32M ZZ TDO NC V DDQ DDQ DDQ DDQ V NC ...
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... V V DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DNU DNU A0 CY7C1372BV25 CY7C1370BV25 CEN ADV/ DDQ DQb SS DD DDQ DQb SS DD DDQ DQb SS DD DDQ DQb SS DD DDQ DQa SS DD DDQ DQa SS DD DDQ DQa SS DD DDQ DQa SS DD ...
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... CE to select/deselect the device and CE to select/deselect the device during the previous clock rise of the Read cycle. The direction controlled by BWS a , and DP is controlled by BWS c d CY7C1372BV25 CY7C1370BV25 controls DQ and DP , BWS controls controls DQ and –DQ are placed in a three-state condition. ...
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... On the next clock rise the data presented to DQ and DP (DQ a,b,c,d CY7C1372BV25) (or a subset for byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. The data written during the Write operation is controlled by ...
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... DQ and DP WE inputs are ignored and the burst counter is incremented. /DP for a,b a,b The correct BWS (BWS for CY7C1372BV25) inputs must be driven in each cycle of the /DP a,b,c,d a,b,c,d burst Write in order to Write the correct bytes of data. for CY7C1372BV25) a,b [ ADV/L CEN ...
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... Write Bytes 2, 1 Write Bytes Write Byte 3 – (DQd and DPd) Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes Write Bytes 3, 2 Write Bytes Write Bytes Write All Bytes Function (CY7C1372BV25) Read Write - No Bytes Written Write Byte 0 - (DQ and Write Byte 1 - (DQ and DP ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370BV25/CY7C1372BV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. Document #: 38-05252 Rev. ** CY7C1372BV25 CY7C1370BV25 When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register ...
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... Note: 10. The “0” or “1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05252 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1372BV25 CY7C1370BV25 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... Boundary Scan Register TAP Controller [8, 9] Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ [10, 11] Over the Operating Range Description / ns CY7C1372BV25 CY7C1370BV25 0 Selection Circuitry Min. Max. 2 0.4 0.2 1.7 V 0 Min. Max. 100 Page TDO ...
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... TDIS t TDIH t TDOV 512K xxxx xxxx 00111 01000 00100 00011 xxxxx xxxxx 00011100100 00011100100 1 1 CY7C1372BV25 CY7C1370BV25 Min. Max ALL INPUT PULSES 2.5V 1.25V t TCYC t TDOX Description Reserved for version number. Defines depth of SRAM. 512K or 1M Defines with of the SRAM. x36 or x18 Reserved for future use ...
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... Do Not Use. This instruction is reserved for future use. Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1372BV25 CY7C1370BV25 Bit Size (x36 ...
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... CEN DQd DQd 2N 27 CLK DPd 1P 28 CE3 MODE 3R 29 BWSa BWSb CE2 CE1 DQb CY7C1372BV25 CY7C1370BV25 Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb 6N 44 DPb 6L 45 MODE 7K 46 ...
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... MHz V > 0. DDQ MAX 6.7-ns cycle, 150 MHz 1/t CYC 7.5-ns cycle, 133 MHz Max Device All speed grades DD Deselected CY7C1372BV25 CY7C1370BV25 0. DDQ [12] Ambient Temperature + – +85 C Min. Max. 2.375 2.625 2.0 0.4 1.7 0.3 0.7 5 -30 30 -30 ...
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... SRAMs when sharing the same EOLZ CHZ CLZ CY7C1372BV25 CY7C1370BV25 Max [15] ALL INPUT PULSES 2.5V 90% 10% GND Rise Time: 1V/ns (c) TQFP Typ. ...
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... CY7C1372BV25 CY7C1370BV25 -150 -133 Max. Min. Max. Unit 1.5 ns 1.5 ns 1.5 ns 1.5 ns 0.5 ns 0.5 ns 0.5 ns 0 ...
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... RA3 RA4 WA5 CHZ Out Out ( for CY7C1370BV25 and for CY7C1372B25) define a Write cyc DON’T CARE = UNDEFINED CY7C1372BV25 CY7C1370BV25 t t CENH CENS CEN HIGH blocks all synchronous inputs RA6 RA7 DOH Out In Out , and CE . All chip enables need to be active ...
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... Document #: 38-05252 Rev CYC WA2 CHZ Q1 Q1+2 Q1+3 Q1+1 Out Out Out define a Write cycle (see Write Cycle Description table and CE . All chip enables need to be active in order to select DON’T CARE = UNDEFINED CY7C1372BV25 CY7C1370BV25 RA3 t CLZ D2+2 D2+3 D2 input signals Out Page ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 22. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05252 Rev EOHZ Three-state I/Os t EOLZ t ZZS I (active DDZZ Three-state CY7C1372BV25 CY7C1370BV25 t EOV t ZZREC Page ...
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... CY7C1372BV25-150BZC 133 CY7C1370BV25-133AC CY7C1372BV25-133AC CY7C1370BV25-133BGC CY7C1372BV25-133BGC CY7C1370BV25-133BZC CY7C1372BV25-133BZC 167 CY7C1370BV25-167AI CY7C1372BV25-167AI CY7C1370BV25-167BGI CY7C1372BV25-167BGI CY7C1370BV25-167BZI CY7C1372BV25-167BZI 150 CY7C1370BV25-150AI CY7C1372BV25-150AI CY7C1370BV25-150BGI CY7C1372BV25-150BGI CY7C1370BV25-150BZI CY7C1372BV25-150BZI 133 CY7C1370BV25-133AI CY7C1372BV25-133AI CY7C1370BV25-133BGI CY7C1372BV25-133BGI CY7C1370BV25-133BZI CY7C1372BV25-133BZI Shaded areas contain advance information. Document #: 38-05252 Rev. ** Package Name Package Type ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05252 Rev. ** CY7C1372BV25 CY7C1370BV25 51-85050-A Page ...
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... Package Diagrams (continued) Document #: 38-05252 Rev. ** 119-lead PBGA (14 × 22 × 2.4 mm) BG119 CY7C1372BV25 CY7C1370BV25 51-85115-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1372BV25 CY7C1370BV25 51-85122-*B ...
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... Document Title: CY7C1370BV25/CY7C1372BV25 512K x 36/ Pipelined SRAM with NoBL™ Architecture Document Number: 38-05252 REV. ECN No. Issue Date ** 113654 Document #: 38-05252 Rev. ** Orig. of Change 05/08/02 CJM Changed from 38-01072 to 38-05252 Added ZZ pin functionality Changed Voh and Vol values to reflect new char. values ...