HDMP-0440 Hewlett-Packard, HDMP-0440 Datasheet

HDMP-0440

Manufacturer Part Number

HDMP-0440

Description

Manufacturer

Hewlett-Packard

Datasheet

1.HDMP-0440.pdf (10 pages)

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Description

The HDMP-0440 is a Quad Port

Bypass Circuit (PBC), which

provides a low-cost, low-power

physical-layer solution for Fibre

Channel Arbitrated Loop (FC-AL)

disk array configurations. By using

a PBC such as the HDMP-0440,

hard disks may be pulled out or

swapped while other disks in the

array are available to the system.

A PBC consists of multiple 2:1

multiplexers daisy chained

together. Each port has two modes

of operation: “disk in loop” and

“disk bypassed.” When the “disk in

loop” mode is selected, the loop

goes into and out of the disk drive

at that port. For example, data goes

from the HDMP-0440’s

TO_NODE[n]

pins to the Disk Drive Transceiver

IC’s (e.g. an HDMP-1636A) Rx

differential input pins. Data from

the Disk Drive Transceiver IC’s Tx

differential outputs goes to the

HDMP-0440’s FM_NODE[n]

differential input pins. Figure 2

CAUTION: As with all semiconductor ICs, it is advised that normal static precautionsb be taken in

the handling and assembly of this component to prevent damage and/or degradation which may be

induced by electrostatic discharge (ESD).

differential output

Agilent HDMP-0440

Quad Port Bypass Circuit

for Fibre Channel Arbitrated Loops

Data Sheet

shows connection diagrams for

disk drive array applications.

When the “disk bypassed” mode

is selected, the disk drive is either

absent or non-functional and the

loop bypasses the hard disk.

The “disk bypassed” mode is

enabled by pulling the

BYPASS[n]- pin low. Leave

BYPASS[n]- floating to enable the

“disk in loop” mode. HDMP-

0440s may be cascaded with

other members of the HDMP-

04XX/HDMP-05XX family

through the appropriate

FM_NODE[n]

TO_NODE[n]

accommodate any number of

hard disks (see Figure 3). The

unused cells in the HDMP-0440

may be bypassed by using

pulldown resistors on the

BYPASS[n]- pins for these cells.

An HDMP-0440 may also be

configured as five 1:1 buffers, as

two 2:1 multiplexers or as two

1:2 buffers.

pins to

and

Features

• Supports 1.0625 GBd Fibre

• Supports 1.25 GBd Gigabit

• Quad PBC in one package

• Equalizers on all inputs

• High-speed LVPECL I/O

• Buffered Line Logic (BLL) outputs

• 0.5 W typical power at V

• 44 Pin, 10 mm, low-cost plastic

Applications

• RAID, JBOD, BTS cabinets

• Two 2:1 muxes

• Two 1:2 buffers

• 1 N Gigabit serial buffer

• N 1 Gigabit serial mux

Channel operation

Ethernet (GE) operation

(no external bias resistors

required)

QFP package

HDMP-0440

= 3.3 V

Related parts for HDMP-0440

HDMP-0440 Summary of contents

Page 1

... Description The HDMP-0440 is a Quad Port Bypass Circuit (PBC), which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0440, hard disks may be pulled out or swapped while other disks in the array are available to the system. ...

Page 2

... EQU EQU TTL EQU BLL BLL 1 0 Figure 1. Block diagram of HDMP-0440. 2 terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. EQU INPUT All FM_NODE[n] high-speed differential inputs have an ...

Page 3

... SERDES EQU EQU TTL EQU TTL BLL BLL BLL Figure 3. Connection diagram for multiple HDMP-0440s. I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output HS_OUT High Speed Output, LVPECL compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground ...

Page 4

Pin Definitions Pin Name Pin Pin Type TO_NODE[0]+ 24 HS_OUT TO_NODE[0]- 25 TO_NODE[1]+ 07 TO_NODE[1]- 06 TO_NODE[2]+ 44 TO_NODE[2]- 43 TO_NODE[3]+ 38 TO_NODE[3]- 37 TO_NODE[4]+ 31 TO_NODE[4]- 30 FM_NODE[0]+ 10 HS_IN FM_NODE[0]- 09 FM_NODE[1]+ 04 FM_NODE[1]- 03 FM_NODE[2]+ 41 FM_NODE[2]- ...

Page 5

Absolute Maximum Ratings except as specified. Operation in excess of any of these conditions may result in permanent damage to this A device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol Parameter ...

Page 6

AC Electrical Specifications + 3. 3. Symbol Parameter T Total Loop Latency from FM_NODE[0] to TO_NODE[0] LOOP_LAT T Per Cell Latency from FM_NODE[4] to TO_NODE[0] CELL_LAT t ...

Page 7

Simplified I/O Cells O_LVTTL V CC ESD PROTECTION GND Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT 75 ESD PROTECTION NOTE: 1. FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure ...

Page 8

... TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER HDMP-0440 TOLERANCE Figure 7. HDMP-0440 package drawing. 8 Units mW C/W for this device is 57ºC/W. is measured on a standard 3x3” FR4 PCB in a still air ja ja Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max 0.10 mm max ...

Page 9

... TO_NODE [1]– 6 TO_NODE [1]+ 7 GND 8 FM_NODE [0]– 9 FM_NODE [0 GND nnnn-nnn = WAFER LOT – BUILD NUMBER; Rz.zz = DIE REVISION SUPPLIER CODE YYWW = DATE CODE ( YY = YEAR WORK WEEK); COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE) Figure 8. HDMP-0440 package layout and marking, top view. GND GND ...

Page 10

For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 ...

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