SAB80C166-M Siemens Semiconductor Group, SAB80C166-M Datasheet

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SAB80C166-M

Manufacturer Part Number
SAB80C166-M
Description
SAB80C166-M16-Bit CMOS Single-Chip Microcontroller
Manufacturer
Siemens Semiconductor Group
Datasheet

Specifications of SAB80C166-M

Case
QFP

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Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
SAB 80C166/83C166
Data Sheet 09.94

Related parts for SAB80C166-M

SAB80C166-M Summary of contents

Page 1

Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller SAB 80C166/83C166 Data Sheet 09.94 ...

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C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary SAB 80C166/83C166 High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable ...

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Introduction The SAB 80C166 is the first representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced IO-capabilities. Figure ...

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Pin Configuration Rectangular P-MQFP-100-2 (top view) Figure 2 Semiconductor Group SAB 80C166 3 SAB 80C166/83C166 ...

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Pin Definitions and Functions Symbol Pin Input Number Output P4.0 – 16-17 I/O P4 XTAL1 20 I XTAL2 19 O BUSACT EBC1 EBC0 24 I RSTIN 27 I RSTOUT 28 O Semiconductor ...

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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output NMI 29 I ALE P1.0 – 30-37 I/O P1.15 40-47 P5.0 – 48-53 I P5.9 56-59 I P2.0 – 62-77 I/O P2.15 62 I/O 75 ...

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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output P3.0 – 80-92, I/O P3.15 95- ...

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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output 38, 61 39, 60, 78, 94 Semiconductor Group Function Digital Supply Voltage during normal operation ...

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Functional Description The architecture of the SAB 80C166 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of ...

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Memory Organization The memory space of the SAB 80C166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address ...

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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...

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A system stack 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two ...

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Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the SAB 80C166 is capable of reacting very fast to the occurrence of non- deterministic events. The ...

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Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 ...

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The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching ...

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Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences channels with a maximum resolution of 400 MHz CPU clock). The CAPCOM unit is typically used to handle high speed ...

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Figure 5 CAPCOM Unit Block Diagram Semiconductor Group SAB 80C166/83C166 16 ...

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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...

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The count direction (up/down) for each timer is programmable by software. For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate e. g. position tracking. Timer T3 has ...

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With its maximum resolution of 200 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock ...

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Parallel Ports The SAB 80C166 provides I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via ...

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Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can ...

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Instruction Set Summary The table below lists the instructions of the SAB 80C166 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, ...

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Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT NOP Semiconductor Group Description Move word ...

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Special Function Registers Overview The following table lists all SFRs which are implemented in the SAB 80C166 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. An SFR can be specified via its individual mnemonic ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address CC7IC b FF86 C3 H CC8 FE90 48 H CC8IC b FF88 C4 H CC9 FE92 49 H CC9IC b FF8A C5 H CC10 FE94 4A H CC10IC b FF8C ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address DPP0 FE00 00 H DPP1 FE02 01 H DPP2 FE04 02 H DPP3 FE06 03 H MDC b FF0E 87 H MDH FE0C 06 H MDL FE0E 07 H ONES ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address S0RIC b FF6E B7 H S0TBUF FEB0 58 H S0TIC b FF6C B6 H S1BG FEBC 5E H S1CON b FFB8 DC H S1EIC b FF76 BB H S1RBUF FEBA ...

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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address T3 FE42 21 H T3CON b FF42 A1 H T3IC b FF62 FE44 22 H T4CON b FF44 A2 H T4IC b FF64 FE46 ...

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Absolute Maximum Ratings Ambient temperature under bias ( SAB 83C166-5M, SAB 80C166-M.................................................................................. ˚C SAB 83C166-5M-T3, SAB 80C166-M-T3 .................................................................. – ˚C T Storage temperature ( ) ....................................................................................... – 150 ˚C ...

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DC Characteristics +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 A Parameter Input ...

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Notes 1) This specification does not apply to the analog input (Port 5.x) which is currently converted. 2) The maximum current may be drawn while the respective signal line remains inactive. 3) The minimum current must be drawn in order ...

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A/D Converter Characteristics +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M- ...

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Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at Figure 9 Input Output Waveforms For timing purposes a port pin is no ...

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AC Characteristics External Clock Drive XTAL1 +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB ...

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AC Characteristics (cont’d) Multiplexed Bus +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 ...

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Parameter Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol Max. CPU Clock = 20 MHz min. max – ...

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ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address t 7 Address t 10 ...

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ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address t 10 ...

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ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address t 7 Address t 9 ...

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ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS RD Write Cycle BUS WR Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address t 7 Address t t ...

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AC Characteristics (cont’d) Demultiplexed Bus +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB 80C166-M-T3 ...

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Parameter ALE rising edge after RD, WR Address hold after RD, WR Semiconductor Group Symbol Max. CPU Clock = 20 MHz min. max - – – ...

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ALE A17-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group Address 6 t ...

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ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group Address t ...

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ALE A17-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group Address 6 t ...

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ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group Address t ...

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AC Characteristics (cont’d) CLKOUT and READY +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB ...

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Running cycle t 32 CLKOUT ALE Command RD, WR Sync READY t 58 Async 3) READY Figure 14 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the ...

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AC Characteristics (cont’d) External Bus Arbitration +70 ˚C for SAB 83C166-5M, SAB 80C166 -40 to +85 ˚C for SAB 83C166-5M-T3, SAB ...

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CLKOUT t 61 HOLD HLDA 1) BREQ Other Signals Figure 15 External Bus Arbitration, Releasing the Bus Notes 1) The SAB 80C166 will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for ...

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CLKOUT HOLD HLDA t 62 BREQ Other Signals Figure 16 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated ...

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