SDA9253 Siemens Semiconductor Group, SDA9253 Datasheet

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SDA9253

Manufacturer Part Number
SDA9253
Description
2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM)
Manufacturer
Siemens Semiconductor Group
Datasheet

Specifications of SDA9253

Case
QFP

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2.6 MBit Dynamic Sequential Access Memory
for Television Applications (TV-SAM)
Preliminary Data
Features
Type
SDA 9253
Semiconductor Group
212
Triple port architecture
One 16
Two 16
Shift registers independently and simultaneously
accessible
Continuous data flow even at maximum speed
40-MHz shift rate – 0.96-Gbit/s total data rate
All inputs and outputs TTL-compatible
Tristate outputs
Random access of groups of 16
of applications
Refresh-free operation possible
5 V
0 … 70 C operating temperature range
Low power dissipation: 700 mW active, 28 mW standby
Suitable for all common TV standards
Allows flicker and noise reduction simultaneously
with only one field memory
Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV
10 % power supply
64
12-bit input shift register
12-bit output shift registers
16
12-bit organization
Ordering Code
Q67101-H5171
12 bits for a wide range
1
P-MQFP-64-1
Package
P-MQFP-64-1
SDA 9253
1998-01-30
CMOS IC

Related parts for SDA9253

SDA9253 Summary of contents

Page 1

MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) Preliminary Data Features 212 64 16 12-bit organization Triple port architecture One 16 12-bit input shift register Two 16 12-bit output shift registers Shift registers independently and simultaneously accessible Continuous ...

Page 2

Functional Description The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate video applications organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the storage of 12-bit ...

Page 3

Data Input (SDC, SCB) Data are shifted in through the serial port C (SDC0, …, SDC11) at the rising edge of the shift clock SCB. After 16 clock pulses the data have to be transferred from shift register C to ...

Page 4

Data Transfer from Latch B to Shift Register B (RB) The contents of latch B are transferred to shift register B at the falling edge of the read transfer signal RB. If the timing restrictions between RB and the shift ...

Page 5

Typical Memory Cycle Sequence A typical application of the TV-SAM is a real-time interfield image processing combined with flicker reduction. This can be achieved, for example, by writing and reading with 13.5-MHz clock rate via port C and B and ...

Page 6

Figure 1 Typical Memory Cycle Sequence Semiconductor Group 6 SDA 9253 1998-01-30 ...

Page 7

Pin Configuration (top view SDC4 49 SDC5 50 SCA 51 SAR 52 SAC 53 SCAD DD1 V 57 SS1 OPM 61 SCB 62 SDC6 63 SDC7 64 ...

Page 8

Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) 34 SQA0 SQA11 O 51 SCA OEA I 44 SQB0 ...

Page 9

SQB 0 12 SQB 11 OEB SCB 12 Shift SDC 0 Register C SDC 11 Latch 212 Figure 3 Block Diagram Semiconductor Group DD1 DD2 ...

Page 10

Absolute Maximum Ratings Parameter Storage temperature Soldering temperature Soldering time Input/output voltage Test function input voltage Power supply voltage Data out current (short circuit) Total power dissipation Power dissipation per output Operating Range Parameter Supply voltage Supply voltage Supply voltage ...

Page 11

DC Characteristics Parameter Symbol Test enable input V IH high voltage Test disable input V IL low voltage V H-output voltage QH L-output voltage V QL ...

Page 12

AC Characteristics Parameter Symbol Memory read write cycle time t RE low time RE t Serial port cycle SC time t RE precharge ...

Page 13

AC Characteristics (cont’ Parameter Symbol lead time t WRL lead time t RWL t Output buffer turn- OFF off delay ...

Page 14

AC Characteristics (cont’ Parameter Symbol Refresh period t REF t Transition time T (rise/fall) L-serial clock time t SCL t H-serial clock time SCH Hold time ...

Page 15

Operation Truth Table RE Cycle N SCAD SAR SAC M0 RA0…RA CA0… RA0…RA CA0… RA0…RA CA0… ...

Page 16

Input conditions : Output conditions Output loading: Diagram 1 AC-Timing Measuring Conditions Semiconductor Group 2 0 ...

Page 17

RE t ROH t ROS SCAD SAR RA6 RA7 RA0 SAC L L CA0 RA t RRL OEA SCA SQA(0-11) Diagram 2 Read Transfer Memory to Port A Semiconductor Group ...

Page 18

RE t ROH t ROS SCAD SAR RA6 RA7 RA0 SAC H L CA0 RB t RRL OEB SCB SQA(0 - 11) Diagram 3 Read Transfer Memory to Port B Semiconductor Group ...

Page 19

RE t ROH t ROS SCAD SAR RA6 RA7 RA0 SAC L H CA0 WT t WTD SCB SDC Diagram 4 Write Transfer from Port C to Memory Semiconductor Group t RC ...

Page 20

Serial Read Operation Port SCA t CAA OEA t OAA SQA(0 - 11) Serial Read Operation Port SCB t CBA OEB t OBA SQB(0 - 11) Serial Write Operation Port SCB ...

Page 21

RE t ROH t ROS SCAD SAR RA6 RA7 RA0 SAC H H CA0 Diagram 6 Refresh with External Row Address Semiconductor Group RA1 RA2 RA3 RA4 CA1 CA2 CA3 ...

Page 22

Application Circuit For best performance and operation within the specified AC parameter limits it is mandatory to use separate decoupling capacitors for V shorted to on the board as shown in figure below. DD2 C Decoupling capacitors and 1 To ...

Page 23

Application Information Digital Storage Field As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with 720 pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit ...

Page 24

Y IN 3ADC Picture + Processor CSG SDA 9206 V IN SYNC SYNC Figure 5 MEGAVISION Block Diagram of Line Flicker Reduction Semiconductor Group SDA9251X 12 SDA 9253 2 12 SDA 9290 SDA 9253 SDA 9251X MSC3 ...

Page 25

Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 25 SDA 9253 Dimensions in mm 1998-01-30 ...

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