CY7C136-35NC Cypress Semiconductor Corporation., CY7C136-35NC Datasheet
CY7C136-35NC
Related parts for CY7C136-35NC
CY7C136-35NC Summary of contents
Page 1
... OE L R/W L [2] INT L Notes: 1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required. Cypress Semiconductor Corporation 2Kx8 Dual-Port Static RAM Functional Description The CY7C132/CY7C136/CY7C142 high-speed CMOS dual-port static RAMs. Two ports are provided to permit independent access to any location in memory ...
Page 2
... Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015 +150 C Latch-Up Current .................................................... >200 mA Operating Range +125 C Range 0.5V to +7.0V Commercial 0.5V to +7.0V Industrial 3.5V to +7.0V [5] Military Note the “instant on” case temperature CY7C132/CY7C136 CY7C142/CY7C146 PQFP Top View 7C136 33 7C146 1415 C132-4 ...
Page 3
... V – 0.2V, CC Mil > V – 0. < 0.2V, [9] MAX Test Conditions MHz 5.0V CC and using AC Test Waveforms input levels of GND to 3V CY7C132/CY7C136 CY7C142/CY7C146 [3] 7C132-30 7C132-35 7C132-45,55 7C136-25,30 7C136-35 7C136-45,55 7C142-30 7C142-35 7C142-45,55 7C146-25,30 7C146-35 7C146-45,55 Min. Max. Min. Max. Min. Max. ...
Page 4
... GND < [6, 11] [3,4] 7C136-15 7C146-15 Min. Max. 15 [12 [12] 15 [12 [10] 0 [10 CY7C132/CY7C136 CY7C142/CY7C146 5V 281 BUSY OR INT 30pF C132-6 C132-5 BUSYOutput Load (CY7C132/CY7C136 ONLY) ALL INPUT PULSES 90% 90% 10% < [3] 7C132-25 7C132-30 7C136-25 7C136-30 7C142-25 7C142-30 7C146-25 7C146-30 Min. Max. Min. Max ...
Page 5
... Min. Max. 15 [16 [16 [17 Note 18 Note [16] 15 [16] 15 [16] 15 [6, 11] 7C132-35 7C136-35 7C142-35 7C146-35 Min. Max. 35 [12 [12] 35 [12 [10] 0 [10 CY7C132/CY7C136 CY7C142/CY7C146 [3] 7C132-25 7C132-30 7C136-25 7C136-30 7C142-25 7C142-30 7C146-25 7C146-30 Min. Max. Min. Max Note Note 18 18 Note Note 7C132-45 ...
Page 6
... PLCC and PQFP versions only. [6, 11] (continued) 7C132-35 7C136-35 7C142-35 7C146- [16 [16 [17 Note 18 Note [16] 25 [16] 25 [16 less than t and t HZCE LZCE HZOE = 5pF as in part ( Test Loads . Transition is measured ±500 mV from steady-state voltage CY7C132/CY7C136 CY7C142/CY7C146 7C132-45 7C132-55 7C136-45 7C136-55 7C142-45 7C142-55 7C146-45 7C146- Note Note 18 ...
Page 7
... OHA DATA OUT PREVIOUS DA TA VALID Read Cycle No. 2 (Either Port-CE/OE LZOE t LZCE DATA OUT Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136) n ADDRESS R R INR t ADDRESS L BUSY L DOUT L Notes: 20. R/W is HIGH for read cycle. 21. Device is continuously selected and ...
Page 8
... If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state. [15, 23 SCE PWE t SD DATA VALID HIGH IMPEDANCE [15, 24 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE allow the data I/O pins to enter high impedance and for data PWE HZWE SD 8 CY7C132/CY7C136 CY7C142/CY7C146 C132- LZWE C132-11 ...
Page 9
... Left Address Valid First: ADDRESS ADDRESS MATCH ADDRESS R BUSY R Right Address Valid First: ADDRESS ADDRESS MATCH ADDRESS L BUSY L ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 9 CY7C132/CY7C136 CY7C142/CY7C146 t BHC C132-12 t BHC C132-13 C132-14 C132-15 ...
Page 10
... Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146 BUSY [19] Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS R INT R Right Side Clears INT : R ADDRESS R INT R t PWE t WC WRITE 7FF t INS HA t EINS t WINS EINR 10 CY7C132/CY7C136 CY7C142/CY7C146 t WH C132-16 C132- READ 7FF t INR t OINR C132-18 ...
Page 11
... Interrupt Timing Diagrams Right Side Sets INT : L ADDRESS R INT L Right Side Clears INT : L ADDRESS R INT L (continued WRITE 7FE t INS HA t EINS t WINS EINR 11 CY7C132/CY7C136 CY7C142/CY7C146 C132- READ 7FE t INR t OINR C132-20 ...
Page 12
... AMBIENTTEMPERATURE(°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4.5V CC 5.0 T =25° 200 400 600 800 1000 CAPACITANCE(pF) 12 CY7C132/CY7C136 CY7C142/CY7C146 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 =5. =25° 1.0 2.0 3.0 4.0 OUTPUTVOLTAGE(V) OUTPUT SINK CURRENT vs ...
Page 13
... CY7C132-45DMB 55 CY7C132-55PC CY7C132-55PI CY7C132-55DMB Speed (ns) Ordering Code 15 CY7C136-15JC CY7C136-15NC 25 CY7C136-25JC CY7C136-25NC 30 CY7C136-30JC CY7C136-30NC CY7C136-30JI 35 CY7C136-35JC CY7C136-35NC CY7C136-35JI CY7C136-35LMB 45 CY7C136-45JC CY7C136-45NC CY7C136-45JI CY7C136-45LMB 55 CY7C136-55JC CY7C136-55NC CY7C136-55JI CY7C136-55LMB Shaded area contains preliminary information. Package Name Package Type P25 48-Lead (600-Mil) Molded DIP P25 ...
Page 14
... Plastic Leaded Chip Carrier L69 52-Square Leadless Chip Carrier J69 52-Lead Plastic Leaded Chip Carrier N52 52-Pin Plastic Quad Flatpack J69 52-Lead Plastic Leaded Chip Carrier L69 52-Square Leadless Chip Carrier 14 CY7C132/CY7C136 CY7C142/CY7C146 Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military ...
Page 15
... MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Max SB1 SB2 SB3 SB4 CY7C132/CY7C136 CY7C142/CY7C146 Switching Characteristics Parameter Subgroups READ CYCLE 10 10 10, 11 ACE 10, 11 DOE WRITE CYCLE 10 10, 11 SCE 10, 11 PWE 10 10 BUSY/INTERRUPT TIMING 10, 11 BLA 10, 11 BHA 10, 11 ...
Page 16
... Package Diagrams 48-Lead (600-Mil) Sidebraze DIP D26 52-Lead Plastic Leaded Chip Carrier J69 16 CY7C132/CY7C136 CY7C142/CY7C146 ...
Page 17
... Package Diagrams (continued) 52-Square Leadless Chip Carrier L69 52-Lead Plastic Quad Flatpack N52 17 CY7C132/CY7C136 CY7C142/CY7C146 ...
Page 18
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead (600-Mil) Molded DIP P25 CY7C132/CY7C136 CY7C142/CY7C146 ...