CY8C26643 Cypress Semiconductor Corporation., CY8C26643 Datasheet
CY8C26643
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CY8C26643 Summary of contents
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... CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet for Silicon Revision D 8-Bit Programmable System-on-Chip (PSoC™) Microcontrollers September 5, 2002 Document #: 38-12010 CY Rev. ** CMS Rev. 3. YPRESS ICRO YSTEMS 1 ...
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... YPRESS ICRO YSTEMS The CY8C25122/CY8C26233/CY8C26443/CY8C26643 family of Programmable System-on- Chip (PSoC™) microcontrollers replaces multiple MCU-based system components with one sin- gle-chip, programmable device. A PSoC microcontroller includes a fast CPU, Flash program memory, and SRAM data memory with configurable analog and digital peripheral blocks in a range of convenient pin-outs and memory sizes ...
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Cypress MicroSystems, Inc. 2000-2002. All rights reserved. PSoC All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress MicroSystems assumes no ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet YPRESS ICRO YSTEMS 4 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 September 5, 2002 ...
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Table of Contents 1.0 Functional Overview ......................................................................................................................14 1.1 Key Features ..............................................................................................................................14 1.2 Pin-out Descriptions ...................................................................................................................15 2.0 CPU Architecture ............................................................................................................................19 2.1 Introduction ................................................................................................................................19 2.2 CPU Registers ...........................................................................................................................20 2.3 Addressing Modes .....................................................................................................................21 2.4 Instruction Set Summary ...........................................................................................................25 3.0 Memory Organization .....................................................................................................................26 3.1 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.8 Analog Continuous Time PSoC Blocks ....................................................................................78 10.9 Analog Switch Cap Type A PSoC Blocks ................................................................................83 10.10 Analog Switch Cap Type B PSoC Blocks ..............................................................................92 10.11 Analog Comparator Bus .........................................................................................................99 10.12 Analog Synchronization .........................................................................................................99 10.13 Analog I/O ............................................................................................................................101 10.14 Analog Modulator .................................................................................................................104 10 ...
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List of Tables Table 1: Device Family Key Features.........................................................................................................14 Table 2: Pin-out 8 Pin .................................................................................................................................15 Table 3: Pin-out 20 Pin ...............................................................................................................................15 Table 4: Pin-out 28 Pin ...............................................................................................................................16 Table 5: Pin-out 44 Pin ...............................................................................................................................16 Table 6: Pin-out 48 Pin ...............................................................................................................................17 Table ...
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... Table 93: Processor Status and Control Register ....................................................................................112 Table 94: Reset WDT Register.................................................................................................................114 Table 95: Voltage Monitor Control Register .............................................................................................116 Table 96: Bandgap Trim Register.............................................................................................................118 Table 97: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) ..........................119 Table 98: Table Read for Supervisory Call Functions ..............................................................................120 Table 99: Flash Program Memory Protection...........................................................................................120 8 Document #: 38-12010 CY Rev ...
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Table 100: Programmer Requirements ....................................................................................................120 Table 101: Absolute Maximum Ratings....................................................................................................125 Table 102: Temperature Specifications....................................................................................................126 Table 103: DC Operating Specifications ..................................................................................................127 Table 104 Operational Amplifier Specifications ...........................................................................128 Table 105: 3.3V DC Operational Amplifier Specifications ........................................................................129 Table 106: DC Analog ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 September 5, 2002 ...
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List of Figures Figure 1: Block Diagram ............................................................................................................................13 Figure 2: CY8C25122 ................................................................................................................................15 Figure 3: CY8C26233 ................................................................................................................................15 Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16 Figure 5: 26643 TQFP ...............................................................................................................................17 Figure 6: 26643 PDIP/SSOP .....................................................................................................................18 Figure 7: General Purpose I/O Pins ..........................................................................................................30 Figure 8: ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 12 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 September 5, 2002 ...
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Analog Input Analog Output Muxing ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 1.0 Functional Overview The CPU heart of this next generation family of micro- controllers is a high performance, 8-bit, M8C Harvard architecture microprocessor. Separate program and memory busses allow for faster overall throughput. Pro- cessor clock speeds to 24 MHz are available. The pro- cessor may also be run at lower clock speeds for power- sensitive applications ...
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Pin-out Descriptions Table 2: Pin-out 8 Pin Name I/O Pin Description P0[7] I/O 1 Port 0[7] (Analog Input) P0[5] I/O 2 Port 0[5] (Analog Input/Output) P1[1] I/O 3 Port 1[1] / XtalIn / SCLK Vss Power 4 Ground P1[0] ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 4: Pin-out 28 Pin Name I/O Pin Description P0[7] I/O 1 Port 0[7] (Analog Input) Port 0[5] (Analog Input/ Out- P0[5] I/O 2 put) Port 0[3] (Analog Input/ Out- P0[3] I/O 3 put) P0[1] I/O 4 Port 0[1] (Analog Input) ...
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Pin-out 44 Pin Table 5: , continued P4[6] I/O 25 Port 4[6] XRES I 26 External Reset P3[0] I/O 27 Port 3[0] P3[2] I/O 28 Port 3[2] P3[4] I/O 29 Port 3[4] P3[6] I/O 30 Port 3[6] Port 2[0] (Non-Multiplexed ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Pin-out 48 Pin Table 6: , continued P5[0] I/O 29 Port 5[0] P5[2] I/O 30 Port 5[2] P4[0] I/O 31 Port 4[0] P4[2] I/O 32 Port 4[2] P4[4] I/O 33 Port 4[4] P4[6] I/O 34 Port 4[6] XRES I 35 External Reset P3[0] I/O 36 Port 3[0] ...
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CPU Architecture 2.1 Introduction This family of microcontrollers is based on a high perfor- mance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 2.2 CPU Registers 2.2.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 8: Flags Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved Reserved Bit 7 : Reserved Bit 6 : Reserved Bit 5 : Reserved ...
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Index Register Table 10: Index Register (CPU_X) Bit # 7 6 POR 0 0 Read System System Write Bit Name Data [7] Data [6] Bit [7:0] : Data [7:0] 8-bit data value holds an index for any ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Examples : ;In this case, the immediate ;value added with the ADD A, 7 ;Accumulator, and the result ;is placed in the ;Accumulator. ;In this case, the immediate MOV X, 8 ;value moved to the X ;register. ;In this case, the immediate ;value logically AND ...
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Examples : ;In this case, the ;value in the memory ;location at address ;7 is added with the ;Accumulator, and the ADD [7], A ;result is placed in ;the memory location ;at address 7. The ;Accumulator is ;unchanged. ;In this ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Examples : ;In this case, the ;value in the memory ;location at address ;X+7 is added with ADD [X+7], 5 ;the immediate value ;of 5, and the result ;is placed in the ;memory location at ;address X+7. ;In this case, the ;immediate value of 6 ;is moved into the ...
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Instruction Set Summary Table 23: Instruction Set Summary (Sorted by Mnemonic) Instruction Format Flags ADC A, expr ADC A, [expr ADC A, [X+expr ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 3.0 Memory Organization 3.1 Flash Program Memory Organization Table 24: Flash Program Memory Map Address Description 0x0000 Reset Vector 0x0004 Supply Monitor Interrupt Vector 0x0008 DBA 00 PSoC Block Interrupt Vector 0x000C DBA 01 PSoC Block Interrupt Vector ...
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Register Bank 0 Map Table 26: Bank 0 PRT0DR 00h 31 RW PRT0IE 01h 31 W PRT0GS 02h 32 W Reserved 03h PRT1DR 04h 31 RW PRT1IE 05h 31 W PRT1GS 06h 32 W Reserved 07h PRT2DR 08h 31 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 4.3 Register Bank 1 Map Table 27: Bank 1 PRT0DM0 00h 32 W PRT0DM1 01h 33 W PRT0IC0 02h 33 W PRT0IC1 03h 34 W PRT1DM0 04h 32 W PRT1DM1 05h 33 W PRT1IC0 06h 33 W PRT1IC1 07h 34 W PRT2DM0 08h 32 W PRT2DM1 09h ...
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I/O Ports 5.1 Introduction Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide I/O port (P5) are implemented. The number of general purpose I/Os implemented and connected to pins depends on the individual part chosen. All port ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet GPIO InterruptEnable (INT_MSK0:5) IM0 IM1 IM0 IM1 IM0 GPIO Read IM1 DM0 DM1 Global Select Bonding Pad DM0 DM1 CPU Bus D Q GPIO Write DM1 Global Out Global Select DM0 DM0 DM1 Figure 7: General Purpose I/O Pins 30 Document #: 38-12010 CY Rev ...
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I/O Registers 6.1 Port Data Registers Table 28: Port Data Registers Bit # 7 6 POR 0 0 Read/Write RW RW Bit Name Data [7] Data [6] Bit [7:0] : Data [7:0] When written is the bits for output ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 6.3 Port Global Select Registers Table 30: Port Global Select Registers Bit # 7 6 POR 0 0 Read/Write W W GlobSel GlobSel Bit Name [7] [6] Bit [7:0] : Global Select [7:0] When written determines whether a pin is connected to the Global Input Bus and Glo- ...
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Port Drive Mode 1 Registers Table 32: Port Drive Mode 1 Registers Bit # 7 6 POR 0 0 Read/Write W W Bit Name DM1 [7] DM1 [6] Bit [7:0] : DM1 [7:0] See truth table for Port Drive ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 6.3.4 Port Interrupt Control 1 Registers Table 34: Port Interrupt Control 1 Registers Bit # 7 6 POR 0 0 Read Write Bit Name IC1 [7] IC1 [6] Bit [7:0] : IC1 [7:0] See truth table for Port Interrupt Control 0 Registers, above Port 0 Interrupt Control 1 Register (PRT0IC1, Address = Bank 1, 03h) ...
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Clocking 7.1 Oscillator Options 7.1.1 Internal Main Oscillator The internal main oscillator outputs two frequencies, 48 MHz and 24 MHz. In the absence of a high-precision input source from the external oscillator, the accuracy of o this circuit is ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 36: Internal Low Speed Oscillator Trim Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved Disable Bit 7 : Reserved Bit 6 : Disable 0 = Low Speed Oscillator Low Speed Oscillator is off (minimum power state) Bit [5:0] : ILO Trim [5:0] Data value stored will alter the trimmed frequency of the Internal Low Speed Oscillator. (Not recommended for customer alteration) 1 ...
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Table 37: External Crystal Oscillator Trim Register Bit # 7 6 POR Read/Write W W Bit Name PSSDC [1] PSSDC [0] Bit [7:6] : PSSDC [1:0] Power System Sleep Duty Cycle. (Not recommended for customer alteration) ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 7.1.5 Phase-Locked Loop (PLL) Operation The Phase-Locked Loop (PLL) function generates the system clock with crystal accuracy designed to pro- vide a 23.986 MHz oscillator when utilized with an exter- nal 32.768 kHz crystal. Although the PLL provides crystal accuracy it requires time to lock onto the refer- ence frequency when first starting ...
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The following diagram shows the PSoC MCU Clock Tree of signals 48M through SLP: PLL Lock Enable IMO Trim Register OSC_CR0[6] IMO_TR[7:0] Internal Oscillator Phase Lock Loop ÷ 732 ECO Trim Register Vcc ECO_TR[7:0] P1[1] External Crystal Oscillator P1[0] ILO ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 40: Oscillator Control 0 Register Bit # 7 6 POR 0 0 Read Write Bit Name 32k Select PLL Mode Bit 7 : 32k Select 0 = Internal low precision 32 kHz oscillator 1 = External Crystal Oscillator Bit 6 : PLL Mode 0 = Disabled 1 = Enabled, Internal Main Oscillator is locked to External Crystal Oscillator ...
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Frequency Selection The following table shows the resulting frequencies for Table 42: 24V1/24V2 Frequency Selection Reg. 24V1 Reg. 24V2 kHz Value MHz Value 00 24.00 24000. 24.00 12000. 24.00 8000. 24.00 6000.00 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 7.2.3 Digital PSoC Block Clocking Options All digital PSoC block clocks are a user-selectable choice of 48M , 24V1 , 24V2 , or 32K , as well as clocking signals from other digital PSoC blocks or general pur- 8.0 Interrupts 8.1 Overview Interrupts can be generated by the General Purpose I/O lines, the Power monitor, the internal Sleep Timer, the eight Digital PSoC blocks, and the four analog columns ...
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R Interrupt IRQ Source S Q IRQ “1” Flip Flop Reset or Decoded Int Ack or Iwrite to INT_VC Register R Interrupt IRQ Source Q IRQ Flip Flop D “1” September 5, 2002 Document #: 38-12010 CY Rev. ** CMS ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 8.2 Interrupt Control Architecture The interrupt controller contains a separate flip-flop for each interrupt. When an interrupt is generated regis- tered as a pending interrupt. It will stay pending until it is serviced, a reset occurs, or there is a write to the INT_VC Register. A pending interrupt will only generate ...
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Interrupt Masks Table 44: General Interrupt Mask Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved Sleep Bit 7 : Reserved Bit 6 : Sleep Interrupt Enable Bit (see 11. Disabled ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 45: Digital PSoC Block Interrupt Mask Register Bit # 7 6 POR 0 0 Read/Write RW RW Bit Name DCA07 DCA06 Bit 7 : DCA07 Interrupt Enable Bit 0 = Disabled 1 = Enabled Bit 6 : DCA06 Interrupt Enable Bit 0 = Disabled 1 = Enabled Bit 5 : DCA05 Interrupt Enable Bit ...
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GPIO Interrupt GPIO Interrupts are polarity configurable and pin-wise maskable (within each Port’s pin configuration registers). They all share the same interrupt priority and vector. Any general purpose I/O can be used as an interrupt source. The GPIO bit ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 9.0 Digital PSoC Blocks 9.1 Introduction PSoC blocks are user configurable system resources. On-chip digital PSoC blocks reduce the need for many MCU part types and external peripheral components. Digital PSoC blocks can be configured to provide a wide variety of peripheral functions ...
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Global Outputs [3:0] Global Inputs [3:0] DBA0 (Basic Block) DCA4 (Comm Block) Global Inputs [7:4] Global Outputs [7:4] Figure 12: Digital Basic and Digital Communications PSoC Blocks *Three of the digital blocks have special functions. DBA3 is a Broadcast block, ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 47: Digital Basic Type A/ Communications Type A Block xx Function Register Bit # 7 6 POR 0 0 Read/Write RW RW Reserved Reserved End Bit Name Bit 7 : Reserved Bit 6 : Reserved Bit 5 : End 0 = PSoC block is not the end of a chained function (End should not be set block DCA07) ...
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Digital Communications Type A Block 05 Function Register Digital Communications Type A Block 06 Function Register Digital Communications Type A Block 07 Function Register 9.2.2 Digital Basic Type A / Communications Type A Block xx Input Register The Digital Basic ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Digital Communications Type A Block 06 Input Register Digital Communications Type A Block 07 Input Register The Data/Enable source select [3:0] bits select between multiple inputs to the Digital PSoC Blocks. These inputs serve as Clock Enables or Data Input depending on the Digital PSoC Block’ ...
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Table 50: Digital Basic Type A / Communications Type A Block xx Output Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved Reserved Bit 7 : Reserved Bit 6 : Reserved Bit 5 : ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 51: Digital Function Outputs Function Primary Output Timer Terminal Count Counter Compare True CRC N/A PRS Serial Data Deadband F0 TX UART TX Data Out RX UART N/A SPI Master MOSI SPI Slave MISO 9.3 Digital PSoC Block Bank 0 Registers ...
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Digital Communications Type A Block 06 Data Register 2 Digital Communications Type A Block 07 Data Register 0 Digital Communications Type A Block 07 Data Register 1 Digital Communications Type A Block 07 Data Register 2 Table 53: R/W Variations ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 9.3.3 Digital Basic Type A/Communications Type A Block xx Control Register 0 When Used as Timer, Counter, CRC, and Deadband Note that the data in this register, as well as the following three registers, are a mapping of the functions of the Table 55: Digital Basic Type A/Communications Type A Block xx Control Register 0... ...
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Digital Communications Type A Block xx Control Register 0 When Used as UART Trans- mitter Table 56: Digital Communications Type A Block xx Control Register 0... Bit # 7 6 POR 0 0 Read Write Bit Name ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 9.3.5 Digital Communications Type A Block xx Control Register 0 When Used as UART Receiver Table 57: Digital Communications Type A Block xx Control Register 0... Bit # 7 6 POR 0 0 Read/Write R R Parity Bit Name Overrun Error Bit 7 : Parity Error 0 = Indicates no parity error detected in the last byte received ...
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Digital Communications Type A Block xx Control Register 0 When Used as SPI Trans- ceiver Table 58: Digital Communications Type A Block xx Control Register 0... Bit # 7 6 POR 0 0 Read Write Bit Name ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 9.4 Global Inputs and Outputs Global Inputs and Outputs provide additional capability to route clock and data signals to the Digital PSoC blocks. Digital PSoC blocks are connected to the global input and output lines by configuring the PSoC block ...
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Timer-configured PSoC blocks may be chained to arbitrary lengths in 8 bit increments. 9.5.1.2 Registers Data Register 1 establishes the period or integer clock division value. Data Register 0 holds the ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 4. Capture vs. Compare A capture event will overwrite Data Register 2. This is also the register that holds the compare value. Therefore, using the capture function may not be compatible with using the timer compare function. 9.5.2 Counter with Optional Compare (Pulse- Width) Output 9 ...
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Disabled State When the Control Register Enable bit is set to ‘0’, the internal block clock is turned off. A write to Data Register 1 (Period) is loaded directly into Data Reg- ister 0 (Counter) to initialize or reset ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 2. Enabling The data input to the Dead-Band function is hard- ware to the primary output of the previous block, which is typically programmed PWM. The proper order for enabling these blocks (writing the Control Register 0) is PWM first, then Dead-Band. ...
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Determining the Polynomial A simple linear-feedback shift register, or LFSR, uses an XOR gate to “add” the values of one or more bits and feed the result back into the least-significant bit. One possible realization of a 6-bit LFSR ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet directly into Data Register 0 (The block must be disabled when writing this value). Data Register 1 specifies the polynomial and width of the numbers in the sequence (see “Specifying the Polynomial”, below). Once the input bit stream is complete, the result may be read by first reading Data Register 0, which returns 0, then reading Data Register 2, which returns the actual result ...
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Inputs A baud-rate clock running at 8 times the desired input bit rate is selected by the clock-input multiplexer The serial data input and clock input are controlled Register (DCA04IN-DCA07IN). 9.5.6.4 Outputs None. 9.5.6.5 Interrupts The function can be ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet except for TX Reg Empty. TX Reg Empty is auto- matically cleared when a byte is written to the TX Data Register (Data Register 1). 3. Using CPU Interrupts TX Reg Empty status or optionally TX Complete sta- tus generates the block interrupt. Executing the interrupt routine does not automatically clear status. ...
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If the SPI Master block is being used to receive data, “dummy” bytes must be written to the TX Data Register in order to initiate transmission/reception of each byte. 9.5.8.3 Inputs MISO (master-in, slave-out) is selected by the input mul- ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet only be input from GPIO input pins (Global Input Bus). There is no way to enable the SS_internally. In SPI modes 2 & 3, where SS is not required between each byte, the external pin may be grounded. Important : The AUX Out Enable bit (bit 5) of the Output Register (DCA04OU-DCA07OU) must be set dis- able it ...
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Analog PSoC Blocks 10.1 Introduction PSoC blocks are user configurable system resources. On-chip analog PSoC blocks reduce the need for many MCU part types and external peripheral components. Analog PSoC blocks can be configured to provide a wide variety ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.2 Analog System Clocking Signals Table 61: Analog System Clocking Signals Signal A system-clocking signal that is driven by the clock output of a digital PSoC block and can be selected ACLK0 by the user to drive the clocking signal to an analog column. Any of the 8 digital PSoC blocks can be muxed into this line using the ACLK0[2:0] bits in the Analog Clock Select Register (CLK_CR1) ...
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Analog Reference and Bias Control The references in the analog array are driven by single op-amps. A single ground referred signal is taken as the reference input and then offset with respect to analog ground. The reference can be ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.6 Analog PSoC Block Clocking Options All analog PSoC blocks in a particular Analog Column share the same clock signal. Choosing the clocking for an analog PSoC block is a two-step process. 1. First, if the user wants to use the ACLK0 and ...
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Analog Clock Select Register Table 64: Analog Clock Select Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved SHDIS Bit 7 : Reserved Bit 6 : SHDIS During normal operation ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet divided into distinct bit fields. Some bit fields set the PSoC block's resistor ratios or capacitor values. Others configure switches and multiplexers that form connec- tions between internal block nodes. Additionally, a block may be connected via local interconnection resources to neighboring analog PSoC blocks, reference voltage sources, input multiplexers and output busses ...
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PMux Port Inputs (1) REFLO (0) ACA 00 (3) (3) AGND AGND (4) ASA 10 ASB 20 10.7.1.3 RBotMux V SS (2) ACA 00 (3) (1) (3) AGND ASA 10 ASB 20 September 5, 2002 Document #: 38-12010 CY ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.8 Analog Continuous Time PSoC Blocks 10.8.1 Introduction The Analog Continuous Time PSoC blocks are built around an operational amplifier. There are several ana- log muxes that are controlled by register-bit settings in the control registers that determine the signal topology inside the block ...
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TestMux REFHI REFLO AGND PMuxOut CompCap Power Block Inputs Port Input ABUS AGND PMux NMux Block Inputs AGND REFHI Gain RTapMux GIN LIN Figure 20: Analog Continuous Time PSoC Blocks 10.8.2 Registers 10.8.2.1 Analog Continuous Time Block xx ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet inverting op-amp input) or for loss (center tap to output of the block). Note that setting Gain alone does not guaran- tee a gain or loss block. Routing of the other ends of the resistor determine this. Table 65: Analog Continuous Time Block xx Control 0 Register ...
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Analog Continuous Time Block xx Control 1 Register The PMux bits control the multiplexing of inputs to the non-inverting input of the op-amp. There are physically only 7 inputs. th The 8 code (111) will leave the input floating. ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.8.2.3 Analog Continuous Time Type A Block xx Control 2 Register CPhase controls which internal clock phase the compar- ator data is latched on. CLatch controls whether the latch is active always transparent. CompCap controls whether the compensation capacitor is switched in or not in the op-amp. By not switching in ...
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Analog Switch Cap Type A PSoC Blocks 10.9.1 Introduction The Analog Switch Cap Type A PSoC blocks are built around an operational amplifier. There are several ana- log muxes that are controlled by register-bit settings in the control registers ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet BQTAP CCap 0.. Inputs ACMux ACap 0..31 C φ Inputs REFHI REFLO φ 2 AGND ARefMux ASign BCap 0..31 C φ Inputs φ 1 BMuxSCA Figure 21: Analog Switch Cap Type A PSoC Blocks 84 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 φ *AutoZero ...
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Local Interconnect 10.9.2.1 AMux ACA 00 ASA 10 RefHi (1) ASB P2.1 20 ABUS0 10.9.2.2 CMux ACA 00 ASA 10 ASB 20 September 5, 2002 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 A Input Multiplexer Connections ACA ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.9.2.3 ACMux The ACMux, as shown in Analog Switch Cap Type A Block xx Control 1 Register, controls the input muxing for both the A and C capacitor branches. The high order bit, ACMux[2], selects one of two inputs for the C branch. 10.9.2.4 ...
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Table 68: Analog Switch Cap Type A Block xx Control 0 Register, continued Bit 7 : FCap F Capacitor value selection bit capacitor units capacitor units Bit 6 : ClockPhase Clock phase select, will ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.9.3.2 Analog Switch Cap Type A Block xx Control 1 Register ACMux controls the input muxing for both the A and C capacitor branches. The high order bit, ACMux[2], selects one of two inputs for the C branch. However, when the bit is high, it also overrides the two low order bits, forcing the A and C branches to the same source ...
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Analog Switch Cap Type A Block xx Control 2 Register AnalogBus gates the output to the analog column bus. The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 70: Analog Switch Cap Type A Block xx Control 2 Register Bit # 7 6 POR 0 0 Read Write Bit Name AnalogBus CompBus Bit 7 : AnalogBus Enable output to the analog bus 0 = Disable output to analog column bus 1 = Enable output to analog column bus (The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register (ASA10CR0, ASA12CR0, ASA21CR0, ASA23CR0) ...
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Analog Switch Cap Type A Block xx Control 3 Register ARefMux selects the reference input of the A capacitor branch. FSW1 is used to control a switch in the integrator capac- itor path. It connects the output of the ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.10 Analog Switch Cap Type B PSoC Blocks 10.10.1 Introduction The Analog Switch Cap Type B PSoC blocks are built around an operational amplifier. There are several ana- log muxes that are controlled by register-bit settings in the control registers that determine the signal topology inside the block ...
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A Mux ACap 0..31 C φ Inputs REFHI REFLO φ 2 AGND ARefMux ASign BCap 0..31 C φ +!BSW 2 B Inputs φ BMuxSCB Figure 25: Analog Switch Cap Type B PSoC Blocks 10.10.2 Registers 10.10.2.1 Analog Switch ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 72: Analog Switch Cap Type B Block xx Control 0 Register, continued Bit 7 : FCap F Capacitor value selection bit capacitor units capacitor units Bit 6 : ClockPhase Clock phase select, will invert clocks internal to the blocks. During normal operation block for the amplifier of a column enabled to drive the output bus, the connection is only made for the last half of PHI2 (during PHI1 and for the first half of PHI2, the output bus floats at the last voltage to which it was driven) ...
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Analog Switch Cap Type B Block xx Control 1 Register AMux controls the input muxing for the A capacitor branch. Table 73: Analog Switch Cap Type B Block xx Control 1 Register Bit # 7 6 POR 0 0 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.10.2.3 Analog Switch Cap Type B Block xx Control 2 Register AnalogBus gates the output to the analog column bus. The output on the analog column bus is affected by the state of the ClockPhase bit in Control 0 Register (ASB11CR0, ASB13CR0, ASB20CR0, ASB22CR0). If AnalogBus is set to 0, the output to the analog column bus is tri-stated ...
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Table 74: Analog Switch Cap Type B Block xx Control 2 Register Bit # 7 6 POR 0 0 Read Write Bit Name AnalogBus CompBus Bit 7 : AnalogBus Enable output to the analog bus 0 = Disable ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.10.2.4 Analog Switch Cap Type B Block xx Control 3 Register ARefMux selects the reference input of the A capacitor branch. FSW1 is used to control a switch in the integrator capac- itor path. It connects the output of the op-amp to the inte- grating cap. The state of the switch is affected by the state of the AutoZero bit in Control 2 Register (ASB11CR2, ASB13CR2, ASB20CR2, ASB22CR2) ...
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Analog Comparator Bus Each analog column has a dedicated comparator bus associated with it. Every analog PSoC block has a com- parator output that can drive out on this bus, but the comparator output from only one analog block ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet The SAR hardware accelerator is a block of specialized hardware designed to sequence the SAR algorithm for efficient A/D conversion. A SAR ADC is implemented conceptually with a DAC of the desired precision, and a comparator. This functionality can be configured from one or more PSoC blocks. For each conversion, the firm- ...
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Analog I/O 10.13.1 Analog Input Muxing MUX ACI0 ACI1 ACM0 BUF AC0 ACA00 ASA10 P2[3] ASB20 P2[1] 10.13.2 Analog Input Select Register This register controls the analog muxes that feed signals in from port pins into each Analog Column. ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 79: Analog Input Select Register Bit # 7 6 POR 0 0 Read Write Bit Name ACI3 [1] ACI3 [0] Bit [7:6] : ACI3 [1: ACM3 P0[ ACM3 P0[ ACM3 P0[ ACM3 P0[6] Bit [5:4] : ACI2 [1: ACM2 P0[ ACM2 P0[ ACM2 P0[ ACM2 P0[7] ACol2Mux (ABF_CR, Address = Bank1, 62h) ...
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Analog Output Buffers The user has the option to output up to four analog sig- nals on the pins of the device. This is done by enabling the analog output buffers associated with each Analog ACA 00 ACA 01 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.13.4 Analog Output Buffer Control Register Table 80: Analog Output Buffer Control Register Bit # 7 6 POR 0 0 Read Write Bit Name ACol1Mux ACol2Mux Bit 7 : ACol1Mux 0 = Set column 1 input to column 1 input mux output 1 = Set column 1 input to column 0 input mux output ...
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Table 81: Analog Modulator Control Register Bit # 7 6 POR 0 0 Read Write Bit Name Reserved Reserved Bit 7 : Reserved Bit 6 : Reserved Bit 5 : Reserved Bit 4 : Reserved Bit [3:2] : ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 10.16 Temperature Sensing Capability A temperature-sensitive voltage derived from the Band Gap sensing on the die is buffered and available as an analog input into the Analog Switch Cap Type A Block ASA21. Temperature sensing allows protection of device operating ranges for fail-safe applications. Temperature ...
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Special Features of the CPU 11.1 Multiplier/Accumulator A fast, on-chip signed 2’s complement MAC (Multiply/ Accumulate) function is provided to assist the main CPU with digital signal processing applications. Multiply results, as well as the lower 2 bytes of ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet MUL_X or MAC_X MULTIPLIER MUL_Y or MAC_Y Figure 28: Multiply/Accumulate Block Diagram Table 82: Multiply Input X Register Bit # 7 6 POR 0 0 Read/Write W W Name Data [7] Data [6] Bit [7:0] : Data [7:0] 8-bit data is the input value for X multiplier Multiply Input X Register (MUL_X, Address = Bank 0, E8h) ...
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Table 84: Multiply Result High Register Bit # 7 6 POR 0 0 Read/Write R R Bit Name Data [7] Data [6] Bit [7:0] : Data [7:0] 8-bit data value is the high order result of the multiply function Multiply ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 88: Accumulator Result 3 / Multiply/Accumulator Clear 0 Register Bit # 7 6 POR 0 0 Read/Write RW RW Bit Name Data [7] Data [6] Bit [7:0] : Data [7:0] 8-bit data value when read is the highest order result of the multiply/accumulate function Any 8-bit data value when written will cause all four Accumulator result registers to clear ...
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This filter is implemented using a combination of hard- ware and software resources. Hardware is used to accu- mulate the high-speed in-coming data while the software Table 90: Decimator/Incremental Control Register Bit # 7 6 POR 0 0 Read/Write RW ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 11.3 Reset 11.3.1 Overview The microcontroller supports two types of resets. When reset is initiated, all registers are restored to their default states and all interrupts are disabled. Reset Types : Power On Reset (POR), External Reset (X ), and Watchdog Reset (WDR). ...
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Power On Reset (POR) Power On Reset (POR) occurs every time the power to the device is switched on. POR is released when the supply is typically 2.2V +/-12% for the upward supply transition, with typically 120mV of hysterisis ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet The Watchdog Timer period is automatically set counts of the Sleep Timer overflows. This represents between two and three sleep intervals depending on the count in the Sleep Timer at the previous WDT clear. When this timer reaches 3, a WDR is generated. ...
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The Stop bit in the Status and Control Register (CPU_SCR) must be cleared for a part to resume out of sleep. Any digital PSoC block that is clocked by a System Clock other ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 11.5 Supply Voltage Monitor The Supply Voltage Monitor detector generates an inter- rupt whenever Vcc drops below a pre-programmed value. There are eight voltage trip points that are select- able by setting the VM [2:0] bit in the Voltage Monitor ...
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Switch Mode Pump This feature is available on the CY8C26xxx versions within this family. During the time Vcc is ramping from 0 Volts to POR V (2.2V +/- 12%), IC operation is held off trip by the POR circuit ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 11.7 Internal Voltage Reference An internal bandgap voltage reference source is pro- vided on-chip. This reference is used for the Supply Volt- age Monitor, and can also be accessed by the user as a reference voltage for analog operations. There is a Bandgap Oscillator Trim Register (BDG_TR) used to cal- ibrate this reference into specified tolerance ...
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... Table 97: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) Operation Function F8h F9h Calibrates then sets Reset PC and SP values to 0 Move block of 64 bytes SP Read Block of FLASH 01 3Ah +3 data into SRAM Program block FLASH with 02 3Ah Write Block +3 data from SRAM Erase block ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 11.8.1 Additional Function for Table Read Supervisory Call The Table Read supervisory operation will return the Ver- sion ID in the Accumulator. The value in the Accumulator is divided into a high and low nibble, indicating major and minor revisions, respectively. Note : The value in the X ...
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Data File Read The user’s data file should be read into the programmer. The checksum should be calculated by the programmer for each record and compared to the record checksum stored in the file for each record. If there ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 11.10.2.6 Device Checksum (at Low Vcc and High Vcc) The device checksum is retrieved from the device and compared to the “Device Checksum” from the user’s file (Note that this is NOT the same thing as the “Record Checksum.” ...
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Development Tools Commands Device Database Application Database Project Database Emulation Pod Figure 34: PSoC Designer Functional Flow 12.1 Overview The Cypress MicroSystems PSoC Designer is a ® Microsoft Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 12.2 Integrated Development Environment Subsystems 12.2.1 Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick ref- erence, each functional subsystem has its own context- sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started ...
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DC and AC Characteristics o Specifications are valid for - 5.25 4.75 3.00 93 kHz Figure 35: CY8C25xxx/CY8C26xxx Voltage Frequency Graph 13.1 Absolute Maximum Ratings Table 101: Absolute Maximum Ratings Symbol Absolute Maximum Ratings Storage Temperature ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 102: Temperature Specifications Symbol Temperature Specifications T Ambient Temperature A T Junction Temperature J 126 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 Minimum Typical Maximum -40 24 +85 -40 100 Unit September 5, 2002 ...
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DC Characteristics Table 103: DC Operating Specifications Symbol DC Operating Specifications V Supply Voltage cc I Supply Current cc I Sleep (Mode) Current sb I Sleep (Mode) Current with Crystal Oscillator sbxtl V Reference Voltage (Bandgap) ref V Input ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 13.2.1 DC Operational Amplifier Specifications 13.2.1.1 5V Specifications The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 5V +/- 5% and -40 ° C <= T <= 85 ° C. The Opera- A tional Amplifier is a component of both the Analog Con- ...
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Specifications The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 3.3V +/- 10% and -40 ° C <= T Operational Amplifier is a component of both the Analog Continuous Time PSoC ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 13.2.2 Analog Input Pin with Multiplexer Specifications Table 106: DC Analog Input Pin with Multiplexer Specifications Symbol DC Analog Input Pin with Multiplexer Specifications Input Leakage (Absolute Value) Input Capacitance Bandwidth Input Voltage Range 13.2.3 Analog Input Pin to Switch Cap Block Specifications ...
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The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 3.3V +/- 10% and -40 ° C <= T parameters apply ° C and are for design guid- ance only. ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 13.2.5 Switch Mode Pump Specifications Table 110: DC Switch Mode Pump Specifications Symbol DC Switch Mode Pump Specifications 1 Output Voltage Available Output Current Short Circuit Current ( Input Voltage Range (During sustained operation) Minimum Input Voltage to Start Pump ...
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DC Analog Reference Specifications The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 5V +/- 5% and -40°C <= TA <= 85°C. The guar- anteed specifications are measured through the Analog Continuous ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 112: 3.3V DC Analog Reference Specifications Symbol 3.3V DC Analog Reference Specifications 1 AGND = Vcc/2 CT Block Bias = High 1 AGND = 2*BandGap CT Block Bias = High AGND = P2[4] (P2[4] = Vcc/2) CT Block Bias = High AGND Column to Column Variation (AGND=Vcc Block Bias = High ...
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DC Programming Specifications Table 114: DC Programming Specifications Symbol DC Programming Specifications I Supply Current During Programming or Verify ccp V Input Low Voltage During Programming or Verify ilp V Input High Voltage During Programming or Verify ihp Input ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 13.3 AC Characteristics Table 115: AC Operating Specifications Symbol AC Operating Specifications F CPU Frequency (5 V Nominal) CPU1 F CPU Frequency (3.3V Nominal) CPU2 F Digital PSoC Block Frequency 48M F Digital PSoC Block Frequency 24M F GPIO Operating Frequency GPIO Internal Main Oscillator Frequency ...
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AC Operational Amplifier Specifications The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 5V +/- 5% and –40 ° C < parameters are provided for design guidance only. Typi- cal ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Table 117: 3.3V AC Operational Amplifier Specifications Symbol 3.3V AC Operational Amplifier Specifications Rising Settling Time to 0.1% Bias = Low Bias = Medium Bias = High Falling Settling Time to 0.1% Bias = Low Bias = Medium Bias = High Rising Slew Rate (20% to 80%) ...
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AC Analog Output Buffer Specifications The following table lists guaranteed maximum and mini- mum specifications for the voltage and temperature ranges, 5V +/- 5% and –40 ° C < Table 118 Analog Output Buffer Specifications ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 13.3.3 AC Programming Specifications Table 120: AC Programming Specifications Symbol AC Programming Specifications T Rise Time of SCLK rsclk T Fall Time of SCLK fsclk T Data Set up Time to Rising Edge of SCLK ssclk T Data Hold Time from Rising Edge of SCLK hsclk F Frequency of SCLK ...
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Packaging Information Figure 36: 44-Lead Thin Plastic Quad Flat Pack A44 September 5, 2002 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 Packaging Information 51-85064-B 141 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Figure 37: 20-Pin Shrunk Small Outline Package O20 142 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 51-85077-B September 5, 2002 ...
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Figure 38: 28-Lead (210-Mil) Shrunk Small Outline Package O28 48 Lead Shrunk Small Outline Package O48 Figure 39: 48-Lead Shrunk Small Outline Package O48 September 5, 2002 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 Packaging Information 51-85079-B 51-85061-C ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Figure 40: 20-Lead (300-Mil) Molded DIP P5 Figure 41: 28-Lead (300-Mil) Molded DIP P21 Figure 42: 48-Lead (600-Mil) Molded DIP P25 144 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 20 Lead (300 Mil) Molded DIP 51-85011-A 51-85014-B 51-85020-A September 5, 2002 ...
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Figure 43: 20-Lead (300-Mil) Molded SOIC S5 Figure 44: 28-Lead (300-Mil) Molded SOIC S21 September 5, 2002 Document #: 38-12010 CY Rev. ** CMS Rev. 3.20 28 Lead (300 Mil) Molded SOIC S21 Packaging Information 51-85024-A 51-85026-A 145 ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet Figure 45: 8-Lead (300-Mil) Molded DIP 14.1 Thermal Impedances per Package Table 121: Thermal Impedances Typical Θ Package JA 8 PDIP 86 C/W 20 PDIP 72 C/W 20 SOIC 78 C/W 20 SSOP 102 C/W 28 PDIP 57 C/W 28 SOIC 61 C/W 28 SSOP 101 C/W 48 PDIP ...
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... CY8C26233-24PVI 8 256 CY8C26443-24PI 16 256 CY8C26443-24SI 16 256 CY8C26443-24PVI 16 256 CY8C26643-24PI 16 256 CY8C26643-24PVI 16 256 CY8C26643-24AI 16 256 Ordering Guide Temperature SMP Range No Ind. -40C to +85C Yes Ind. -40C to +85C Yes Ind. -40C to +85C Yes Ind. -40C to +85C Yes Ind. -40C to +85C Yes Ind. -40C to +85C Yes Ind ...
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... Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet 16.0 Document Revision History Table 123: Document Revision History Document Title : CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet for Silicon Revision D Document Number : 38-12010 Revision ECN # Issue Date ** 116628 6/17/2002 Distribution : External/Public Posting : None 148 Document #: 38-12010 CY Rev ...