MC9S12DG256 Motorola, MC9S12DG256 Datasheet
MC9S12DG256
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MC9S12DG256 Summary of contents
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... Motorola was negligent regarding the design or manufacture of the part. MC9S12DT256 V03.03 Covers also MC9S12DG256, Revised:26 July 2003 Motorola, Inc 9S12DT256DGV3/D 1 ...
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized ...
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MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.03 3 ...
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MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.03 4 ...
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Table of Contents Section 1 IntroductionMC9S12DT256 1.1 Overview ...
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MC9S12DT256 Device User Guide — V03.03 2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin ...
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PS0 / RXD0 — Port S I/O Pin ...
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MC9S12DT256 Device User Guide — V03.03 6.1 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Appendix A Electrical Characteristics A.1 General ...
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MC9S12DT256 Device User Guide — V03.03 10 ...
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List of Figures Figure 0-1 Order Partnumber Example ...
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MC9S12DT256 Device User Guide — V03.03 12 ...
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List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MC9S12DT256 Device User Guide — V03.03 Table A-21 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... LQFP/80 QFP L91N PV/FU An errata exists contact Sales Office Package Option Temperature Option Device Title Controller Family MC9S12DT256 Device User Guide — V03.03 MC9S12DJ256 MC9S12DG256 2 2 — — — 112 LQFP/80 QFP 112 LQFP/80 QFP L91N L91N PV/FU PV/FU An errata exists ...
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MC9S12DT256 Device User Guide — V03.03 The following items should be considered when using a derivative (Table 0-1): • Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without ...
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... K Byte Flash (FTS256K) Block User Guide 4K Byte EEPROM (EETS4K) Block User Guide Byte Level Data Link Controller -J1850 (BDLC) Block User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG) Block User Guide Port Integration Module (PIM_9DP256) Block User Guide Table 0-3 shows the Specification Change Summary for Maskset L91N. Table 0-3 Specifi ...
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MC9S12DT256 Device User Guide — V03.03 Table 0-3 Specification Change Summary for Maskset L91N Block EETS4K/FTS256K PIM_9DP256 18 Spec Change Reliability Specification for Non Volatile Memories CAN0 can be routed to PORTJ ...
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User Guide End Sheet MC9S12DT256 Device User Guide — V03.03 129 ...
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MC9S12DT256 Device User Guide — V03.03 130 FINAL PAGE OF 130 PAGES ...
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Section 1 IntroductionMC9S12DT256 1.1 Overview The MC9S12DT256 microcontroller unit (MCU 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, ...
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MC9S12DT256 Device User Guide — V03.03 – Programmable rising or falling edge trigger • Memory – 256K Flash EEPROM – 4K byte EEPROM – 12K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability ...
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... Emulation Expanded Narrow Mode • Special Operating Modes – Special Single-Chip Mode with active Background Debug Mode – Special Test Mode (Motorola use only) – Special Peripheral Mode (Motorola use only) Low power modes • Stop Mode • Pseudo Stop Mode • ...
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MC9S12DT256 Device User Guide — V03.03 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT256 device. 22 ...
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Figure 1-1 MC9S12DT256 Block Diagram 256K Byte Flash EEPROM 12K Byte RAM 4K Byte EEPROM VDDR VSSR VREGEN Voltage Regulator VDD1,2 VSS1,2 Single-wire Background BKGD CPU12 Debug Module XFC Clock and VDDPLL Reset PLL Periodic Interrupt VSSPLL Generation COP Watchdog ...
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... Serial Peripheral Interface (SPI2) $0100- $010F $0110 - $011B $011C - $011F Reserved $0120 - $013F $0140 - $017F $0180 - $01BF Motorola Scalable Can (CAN1) $01C0 - $01FF Reserved $0200 - $023F $0240 - $027F $0280 - $02BF Motorola Scalable Can (CAN4) $02C0 - $03FF Reserved $0000 - $0FFF EEPROM array ...
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Table 1-1 Device Memory Map Address $1000 - $3FFF RAM array Fixed Flash EEPROM array $4000 - $7FFF incl. 0.5K, 1K Protected Sector at start $8000 - $BFFF Flash EEPROM Page Window Fixed Flash EEPROM array incl. ...
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MC9S12DT256 Device User Guide — V03.03 Figure 1-2 MC9S12DT256 Memory Map $0000 $0400 $1000 $4000 $8000 EXTERN $C000 $FF00 VECTORS VECTORS $FFFF EXPANDED* NORMAL SINGLE CHIP * Assuming that a ‘0’ was driven onto port K bit 7 during MCU ...
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Detailed Register Map The following tables show the detailed register map of the MC9S12DT256. $0000 - $000F Address Name Read: $0000 PORTA Write: Read: $0001 PORTB Write: Read: $0002 DDRA Write: Read: $0003 DDRB Write: Read: $0004 Reserved Write: ...
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MC9S12DT256 Device User Guide — V03.03 $0010 - $0014 Address Name Read: $0012 INITEE Write: Read: $0013 MISC Write: Read: $0014 Reserved Write: $0015 - $0016 Address Name Read: $0015 ITCR Write: Read: $0016 ITEST Write: $0017 - $0017 Address ...
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MEBI map (Core User Guide) Address Name Bit 7 Read: $001E IRQE INTCR Write: $001F - $001F INT map (Core User Guide) Address Name Bit 7 Read: $001F HPRIO PSEL7 Write: ...
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MC9S12DT256 Device User Guide — V03.03 $0028 - $002F Address Name Read: $002D BKP1X Write: Read: $002E BKP1H Write: Read: $002F BKP1L Write: $0030 - $0031 Address Name Read: $0030 PPAGE Write: Read: $0031 Reserved Write: $0032 - $0033 Address ...
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CRG (Clock and Reset Generator) Address Name Bit 7 FORBYP Read: $003D RTIBYP COPBYP TEST ONLY Write: CTCTL Read: TCTL7 $003E TEST ONLY Write: Read: $003F ARMCOP Write: Bit 7 $0040 - $007F ECT (Enhanced Capture Timer ...
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MC9S12DT256 Device User Guide — V03.03 $0040 - $007F Address Name Read: $0053 TC1 (lo) Write: Read: $0054 TC2 (hi) Write: Read: $0055 TC2 (lo) Write: Read: $0056 TC3 (hi) Write: Read: $0057 TC3 (lo) Write: Read: $0058 TC4 (hi) ...
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ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Read: $006C Reserved Write: TIMTST Read: $006D Test Only Write: Read: $006E Reserved Write: Read: $006F Reserved Write: Read: $0070 PBCTL Write: Read: $0071 PBFLG ...
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MC9S12DT256 Device User Guide — V03.03 $0080 - $009F Address Name Read: $0082 ATD0CTL2 Write: Read: $0083 ATD0CTL3 Write: Read: $0084 ATD0CTL4 Write: Read: $0085 ATD0CTL5 Write: Read: $0086 ATD0STAT0 Write: Read: $0087 Reserved Write: Read: $0088 ATD0TEST0 Write: Read: ...
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ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Read: $009B ATD0DR5L Write: Read: Bit15 $009C ATD0DR6H Write: Read: $009D ATD0DR6L Write: Read: Bit15 $009E ATD0DR7H Write: Read: $009F ATD0DR7L Write: $00A0 - ...
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MC9S12DT256 Device User Guide — V03.03 $00A0 - $00C7 Address Name Read: $00B1 PWMCNT5 Write: Read: $00B2 PWMCNT6 Write: Read: $00B3 PWMCNT7 Write: Read: $00B4 PWMPER0 Write: Read: $00B5 PWMPER1 Write: Read: $00B6 PWMPER2 Write: Read: $00B7 PWMPER3 Write: Read: ...
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SCI0 (Asynchronous Serial Interface) Address Name Bit 7 Read: $00C8 SCI0BDH Write: Read: $00C9 SBR7 SCI0BDL Write: Read: $00CA LOOPS SCISWAI SCI0CR1 Write: Read: $00CB SCI0CR2 Write: Read: TDRE $00CC SCI0SR1 Write: Read: $00CD SCI0SR2 Write: Read: ...
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MC9S12DT256 Device User Guide — V03.03 $00D8 - $00DF Address Name Read: $00DC Reserved Write: Read: $00DD SPI0DR Write: Read: $00DE Reserved Write: Read: $00DF Reserved Write: $00E0 - $00E7 Address Name Read: $00E0 IBAD Write: Read: $00E1 IBFD Write: ...
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SPI1 (Serial Peripheral Interface) Address Name Bit 7 Read: $00F0 SPIE SPI1CR1 Write: Read: $00F1 SPI1CR2 Write: Read: $00F2 SPI1BR Write: Read: SPIF $00F3 SPI1SR Write: Read: $00F4 Reserved Write: Read: $00F5 SPI1DR Write: Read: $00F6 Reserved ...
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MC9S12DT256 Device User Guide — V03.03 $0100 - $010F Address Name Read: $0104 FPROT Write: Read: $0105 FSTAT Write: Read: $0106 FCMD Write: Reserved for Read: $0107 Factory Test Write: Read: $0108 FADDRHI Write: Read: $0109 FADDRLO Write: Read: $010A ...
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EEPROM Control Register (eets4k) Address Name Bit 7 Read: $0119 EADDRLO Bit 7 Write: Read: $011A Bit 15 EDATAHI Write: Read: $011B Bit 7 EDATALO Write: $011C - $011F Reserved for RAM Control Register Address Name Bit ...
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... Bit7 Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 Bit15 Bit7 Bit6 0 CAN0 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 Bit 3 Bit 2 Bit ...
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... CAN0 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $0143 CAN0BTR1 SAMP Write: Read: $0144 WUPIF CAN0RFLG Write: Read: $0145 WUPIE CAN0RIER Write: Read: $0146 CAN0TFLG Write: Read: $0147 CAN0TIER Write: Read: $0148 CAN0TARQ Write: Read: $0149 CAN0TAAK Write: ...
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MC9S12DT256 Device User Guide — V03.03 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Extended ID Read: $xxx2 Standard ID Read: CANxRIDR2 Write: Extended ID Read: $xxx3 Standard ID Read: CANxRIDR3 Write: Read: $xxx4- CANxRDSR0 - ...
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... CAN1 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $0180 RXFRM CAN1CTL0 Write: Read: $0181 CANE CAN1CTL1 Write: Read: $0182 SJW1 CAN1BTR0 Write: Read: $0183 SAMP CAN1BTR1 Write: Read: $0184 WUPIF CAN1RFLG Write: Read: $0185 WUPIE CAN1RIER Write: Read: ...
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... PTS Write: Read: $0249 PTIS Write: Read: $024A DDRS Write: Read: $024B RDRS Write: Read: $024C PERS Write: 46 CAN1 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 AC7 AC6 AC5 AC4 AC7 AC6 AC5 AC4 AC7 AC6 AC5 AC4 AM7 AM6 ...
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PIM (Port Integration Module PIM_9DP256) Address Name Bit 7 Read: $024D PPSS PPSS7 Write: Read: $024E WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 WOMS Write: Read: $024F Reserved Write: Read: $0250 PTM PTM7 Write: Read: PTIM7 ...
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... DDRJ7 DDRJ7 0 RDRJ7 RDRJ6 0 PERJ7 PERJ6 0 PPSJ7 PPSJ6 0 PIEJ7 PIEJ6 0 PIFJ7 PIFJ6 CAN4 (Motorola Scalable CAN - MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 RXACT SYNCH RXFRM CSWAI CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 ...
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... CAN4 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Read: $028C Reserved Write: Read: $028D Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 $028E CAN4RXERR Write: Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 $028F CAN4TXERR ...
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MC9S12DT256 Device User Guide — V03.03 $02C0 - $03FF Address Name Read: $02C0 Reserved - $03FF Write: 1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The ...
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... Device Pinout The MC9S12DT256/MC9S12DJ256/MC9S12DG256 and MC9S12A256 is available in a 112-pin low profile quad flat pack (LQFP) and MC9S12DJ256/MC9S12DG256 and MC9S12A256 is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 and Figure 2-2 show the pin assignments. ...
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... IOC6/PT6 17 IOC7/PT7 18 XADDR19/PK5 19 XADDR18/PK4 20 KWJ1/PJ1 21 KWJ0/PJ0 22 MODC/TAGHI/BKGD 23 ADDR0/DATA0/PB0 24 ADDR1/DATA1/PB1 25 ADDR2/DATA2/PB2 26 ADDR3/DATA3/PB3 27 ADDR4/DATA4/PB4 28 Figure 2-1 Pin Assignments in 112-pin LQFP 52 MC9S12DT256/MC9S12A256/ MC9S12DJ256/MC9S12DG256 Signals shown in Bold are not available on the 80 Pin Package 84 VRH 83 VDDA 82 PAD15/AN15/ETRIG1 81 PAD07/AN07/ETRIG0 80 PAD14/AN14 79 PAD06/AN06 78 PAD13/AN13 77 PAD05/AN05 76 PAD12/AN12 75 PAD04/AN04 74 PAD11/AN11 73 PAD03/AN03 72 ...
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SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DJ256 2.2 Signal Properties Summary Table 2-1summarizes the pin functionality. Signals shown ...
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MC9S12DT256 Device User Guide — V03.03 Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 EXTAL — — XTAL — — RESET — — TEST — — VREGEN — — XFC — — BKGD TAGHI MODC PAD[15] ...
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Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 PH4 KWH4 MISO2 PH3 KWH3 SS1 PH2 KWH2 SCK1 PH1 KWH1 MOSI1 PH0 KWH0 MISO1 PJ7 KWJ7 TXCAN4 PJ6 KWJ6 RXCAN4 PJ[1:0] KWJ[1:0] — PK7 ECS ROMONE XADDR ...
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MC9S12DT256 Device User Guide — V03.03 Pin Name Pin Name Pin Name Funct. 1 Funct. 2 Funct. 3 PP4 KWP4 PWM4 PP3 KWP3 PWM3 PP2 KWP2 PWM2 PP1 KWP1 PWM1 PP0 KWP0 PWM0 PS7 SS0 — PS6 SCK0 — PS5 ...
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... This input only pin enables or disables the on-chip voltage regulator. 2.3.5 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. ...
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MC9S12DT256 Device User Guide — V03.03 2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can act ...
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Figure 2-4 Colpitts Oscillator Connections (PE7=1) EXTAL MCU XTAL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC ...
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MC9S12DT256 Device User Guide — V03.03 Figure 2-6 External Clock Connections (PE7=0) 2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin used as a MCU operating ...
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PE2 / R/W — Port E I/O Pin 2 PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction ...
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... PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial data pin SDA of the IIC module. ...
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... PM4 / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4 PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). 2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 — ...
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... PM0 / RXCAN0 / RXB — Port M I/O Pin 0 PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin RXB of the BDLC. 2.3.42 PP7 / KWP7 / PWM7 / SCK2 — Port P I/O Pin 7 PP7 is a general purpose input or output pin ...
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PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. ...
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MC9S12DT256 Device User Guide — V03.03 2.3.55 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). ...
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VDD1, VDD2, VSS1, VSS2 — Core Power Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place ...
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MC9S12DT256 Device User Guide — V03.03 Pin Number Mnemonic 112-pin QFP V 43 DDPLL V 45 SSPLL VREGEN 97 2.4.7 VREGEN — On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied ...
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Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block ...
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MC9S12DT256 Device User Guide — V03.03 70 ...
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Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DT256. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for ...
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MC9S12DT256 Device User Guide — V03.03 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS VREGEN 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: ...
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Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. ...
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MC9S12DT256 Device User Guide — V03.03 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. 74 ...
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Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of ...
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MC9S12DT256 Device User Guide — V03.03 $FFD0, $FFD1 $FFCE, $FFCF $FFCC, $FFCD Modulus Down Counter underflow $FFCA, $FFCB Pulse Accumulator B Overflow $FFC8, $FFC9 $FFC6, $FFC7 CRG Self Clock Mode $FFC4, $FFC5 $FFC2, $FFC3 $FFC0, $FFC1 $FFBE, $FFBF $FFBC, $FFBD ...
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Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 5.3.1 I/O pins Refer to the HCS12 Core User ...
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Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU. When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods. 6.2 HCS12 Module Mapping Control ...
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MC9S12DT256 Device User Guide — V03.03 6.6 HCS12 Breakpoint (BKP) Block Description Consult the BKP Block guide for information on HCS12 breakpoint block Section 7 Clock and Reset Generator (CRG) Block Description Consult the CRG Block User Guide for information ...
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... Flash. Exact details of the changeover (i.e. blank to programmed) for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device. Please contact Motorola SPS Sales if you have any additional questions. Consult the FTS256K Block User Guide for information about the flash module. Section 16 EEPROM 4K Block Description MC9S12DT256 Device User Guide — ...
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... Section 18 MSCAN Block Description There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT256. Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. Section 19 Port Integration Module (PIM) Block Description Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module. ...
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Component C10 / C P C11 / The PCB must be carefully laid out ...
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MC9S12DT256 Device User Guide — V03.03 Figure 20-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VDD1 C1 VSS1 84 VSSX VSSR VDDR Q1 VSSPLL VDDPLL R1 VSSA C3 VDDA VSS2 C2 VDD2 ...
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Figure 20-2 Recommended PCB Layout for 80QFP Colpitts Oscillator VDD1 C1 VSS1 VSSR VDDR MC9S12DT256 Device User Guide — V03.03 C3 VSSA VSSX Q1 VSSPLL VDDPLL R1 VDDA VSS2 C2 VDD2 85 ...
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MC9S12DT256 Device User Guide — V03.03 Figure 20-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VDD1 C1 VSS1 86 VSSX VSSR R3 VDDR R2 Q1 VDDPLL R1 VSSA C3 VDDA VSS2 C2 VDD2 VSSPLL ...
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Figure 20-4 Recommended PCB Layout for 80QFP Pierce Oscillator VSSX VDD1 C1 VSS1 VSSR VDDR MC9S12DT256 Device User Guide — V03.03 C3 VSSA VDDA VSS2 C2 VDD2 VSSPLL VSSPLL VDDPLL R1 87 ...
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MC9S12DT256 Device User Guide — V03.03 88 ...
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... A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Motorola and are subject to change without notice. This supplement contains the most accurate electrical information for the MC9S12DT256 microcontroller available at the time of publication. The information should be considered to change ...
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MC9S12DT256 Device User Guide — V03.03 The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply ...
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A.1.4 Current Injection Power supply must maintain regulation within operating V operating maximum current conditions. If positive injection current (V injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external ...
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MC9S12DT256 Device User Guide — V03.03 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. ...
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A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device ( with regards to the ...
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MC9S12DT256 Device User Guide — V03. Junction Temperature Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can ...
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Table A-5 Thermal Package Characteristics Num C Rating 1 T Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB with 2 internal planes 3 T Thermal Resistance LQFP 80, single sided PCB Thermal Resistance ...
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MC9S12DT256 Device User Guide — V03.03 Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P Input High Voltage T Input High Voltage 2 P Input Low Voltage T Input Low Voltage 3 C Input Hysteresis ...
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A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip ...
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MC9S12DT256 Device User Guide — V03.03 given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise ...
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A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results ...
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MC9S12DT256 Device User Guide — V03.03 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of ...
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A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted ...
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MC9S12DT256 Device User Guide — V03.03 DNL LSB V i-1 $3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 NOTE: ...
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A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. ...
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MC9S12DT256 Device User Guide V03.03 A.3.1.3 Sector Erase Erasing a 512 byte Flash sector byte EEPROM sector takes: The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: The setup ...
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Maximum Erase and Programming times are achieved under particular combinations of f Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Burst Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum ...
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A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL ...
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A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can ...
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MC9S12DT256 Device User Guide — V03.03 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal ...
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A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the ...
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MC9S12DT256 Device User Guide — V03.03 The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, C typical values are 50. = 0.9 ensures a good transient response. f < ...
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The relative deviation its maximum for one clock period, and decreases towards zero for larger nom number of clock periods (N). Defining the jitter as For ...
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MC9S12DT256 Device User Guide — V03.03 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Conditions are shown in Table A-4 unless otherwise ...
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A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating 1 P MSCAN Wake-up dominant pulse filtered 2 P MSCAN Wake-up dominant pulse pass MC9S12DT256 Device User Guide — V03.03 ...
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A.7 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-18 the measurement conditions are listed. Description Drive mode Load capacitance C LOAD, on all outputs Thresholds for delay measurement points A.7.1 Master Mode In Figure ...
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MC9S12DT256 Device User Guide — V03. (OUTPUT) 2 SCK (CPOL 0) (OUTPUT) 4 SCK (CPOL 1) (OUTPUT) 5 MISO MSB IN (INPUT) 9 MOSI PORT DATA MASTER MSB OUT (OUTPUT) 1.If configured as output 2. LSBF = 0. ...
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A.7.2 Slave Mode In Figure A-7 the timing diagram for slave mode with transmission format CPHA=0 is depicted. SS (INPUT) SCK (CPOL 0) (INPUT) 2 SCK (CPOL 1) 10 (INPUT) 7 MISO see SLAVE MSB (OUTPUT) note 5 MOSI MSB ...
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MC9S12DT256 Device User Guide — V03.03 SS (INPUT) 2 SCK (CPOL 0) (INPUT) 4 SCK (CPOL 1) (INPUT) 9 MISO see SLAVE note (OUTPUT MOSI MSB IN (INPUT) NOTE: Not defined! Figure A-8 SPI Slave Timing (CPHA=1) In ...
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A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-21. All major bus signals are included in the diagram. While both a data write ...
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MC9S12DT256 Device User Guide — V03.03 ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA Non-Multiplexed Addresses PK5:0 ECS PK7 24 R/W PE2 27 LSTRB PE3 30 NOACC PE7 33 IPIPO0 IPIPO1, PE6,5 Figure ...
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Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 1 P Frequency of operation (E-clock Cycle time 3 D Pulse width, E low Pulse width, ...
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MC9S12DT256 Device User Guide — V03.03 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C Num C Rating 32 D NOACC hold time 33 D IPIPO[1:0] delay time D IPIPO[1:0] valid time to ...
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Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DT256 packages. MC9S12DT256 Device User Guide — V03.03 125 ...
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MC9S12DT256 Device User Guide — V03.03 B.2 112-pin LQFP package 0. PIN 1 112 IDENT 1 VIEW 0.050 C1 VIEW AB Figure B-1 112-pin LQFP mechanical ...
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B.3 80-pin QFP package 0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W X DETAIL C Figure B-2 80-pin QFP Mechanical Dimensions (case no. 841B) L ...
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