MC68HC11F1VFN4 Freescale Semiconductor, Inc, MC68HC11F1VFN4 Datasheet
MC68HC11F1VFN4
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... Freescale Semiconductor © Freescale Semiconductor, Inc., 2004. All rights reserved. HC11 MC68HC11F1 Technical Data ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...
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... Freescale Semiconductor, Inc. Paragraph 1.1 Features .................................................................................................... 1-1 SECTION 2 PIN DESCRIPTIONS 2.1 V and V .............................................................................................. 2 2.2 Reset (RESET) .......................................................................................... 2-3 2.3 E-Clock Output (E) .................................................................................... 2-3 2.4 Crystal Driver and External Clock Input (XTAL, EXTAL) ........................... 2-3 2.5 Four Times E-Clock Frequency Output (4XOUT) ..................................... 2-5 2.6 Interrupt Request (IRQ) ............................................................................. 2-5 2 ...
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... Freescale Semiconductor, Inc. Paragraph 3.2 Data Types ................................................................................................ 3-7 3.3 Opcodes and Operands ............................................................................ 3-7 3.4 Addressing Modes ..................................................................................... 3-7 3.4.1 Immediate .......................................................................................... 3-7 3.4.2 Direct ................................................................................................. 3-8 3.4.3 Extended ........................................................................................... 3-8 3.4.4 Indexed .............................................................................................. 3-8 3.4.5 Inherent ............................................................................................. 3-8 3.4.6 Relative ............................................................................................. 3-8 3.5 Instruction Set ........................................................................................... 3-8 SECTION 4OPERATING MODES AND ON-CHIP MEMORY 4 ...
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... Freescale Semiconductor, Inc. Paragraph 4.5 Chip Selects ............................................................................................ 4-18 4.5.1 Program Chip Select ....................................................................... 4-18 4.5.2 I/O Chip Selects .............................................................................. 4-18 4.5.3 General-Purpose Chip Select .......................................................... 4-19 SECTION 5 RESETS AND INTERRUPTS 5.1 Resets ....................................................................................................... 5-1 5.1.1 Power-On Reset ................................................................................ 5-1 5.1.2 External Reset (RESET) ................................................................... 5-1 5.1.3 Computer Operating Properly (COP) Reset ...................................... 5-2 5 ...
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... Freescale Semiconductor, Inc. Paragraph 6.2 Port B ........................................................................................................ 6-2 6.3 Port C ........................................................................................................ 6-2 6.4 Port D ........................................................................................................ 6-3 6.5 Port E ........................................................................................................ 6-4 6.6 Port F ......................................................................................................... 6-4 6.7 Port G ........................................................................................................ 6-5 6.8 System Configuration Options 2 ................................................................ 6-5 SECTION 7 SERIAL COMMUNICATIONS INTERFACE 7.1 Data Format .............................................................................................. 7-1 7.2 Transmit Operation .................................................................................... 7-1 7.3 Receive Operation ..................................................................................... 7-2 7 ...
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... Freescale Semiconductor, Inc. Paragraph SECTION 9 TIMING SYSTEM 9.1 Timer Structure .......................................................................................... 9-3 9.2 Input Capture ............................................................................................. 9-5 9.2.1 Timer Control Register 2 ................................................................... 9-5 9.2.2 Timer Input Capture Registers .......................................................... 9-6 9.2.3 Timer Input Capture 4/Output Compare 5 Register .......................... 9-6 9.3 Output Compare ........................................................................................ 9-6 9.3.1 Timer Output Compare Registers ..................................................... 9-7 9 ...
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... Freescale Semiconductor, Inc. Paragraph 10.7 Operation in STOP and WAIT Modes .................................................... 10-7 10.8 A/D Control/Status Registers .................................................................. 10-7 10.9 A/D Converter Result Registers .............................................................. 10-8 APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX BMECHANICAL DATA AND ORDERING INFORMATION B.1 Pin Assignments ....................................................................................... B-1 B.2 Package Dimensions ................................................................................ B-2 B.3 Ordering Information ................................................................................ B-3 APPENDIX CDEVELOPMENT SUPPORT C ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure 1-1 MC68HC11F1 Block Diagram ........................................................................ 1-2 2-1 Pin Assignments for MC68HC11F1 68-Pin PLCC ......................................... 2-1 2-2 Pin Assignments for MC68HC11F1 80-Pin QFP ............................................ 2-2 2-3 External Reset Circuit ..................................................................................... 2-3 2-4 Common Crystal Connections ........................................................................ 2-4 2-5 External Oscillator Connections ..................................................................... 2-4 2-6 One Crystal Driving Two MCUs ...
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... Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Figure A-11 SPI Master Timing (CPHA = 1) .................................................................... A-15 A-12 SPI Slave Timing (CPHA = 0) ...................................................................... A-16 A-13 SPI Slave Timing (CPHA = 1) ...................................................................... A-16 B-1 MC68HC11F1 68-Pin PLCC .......................................................................... B-1 B-2 MC68HC11F1 80-Pin Quad Flat Pack ........................................................... B-2 For More Information On This Product, ...
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... Freescale Semiconductor, Inc. Table 2-1 Port Signal Functions ...................................................................................... 2-7 3-1 Reset Vector Comparison ............................................................................... 3-5 3-2 Instruction Set ................................................................................................. 3-9 4-1 Register and Control Bit Assignments............................................................. 4-5 4-2 Write Access Limited Registers....................................................................... 4-7 4-3 Hardware Mode Select Summary ................................................................... 4-7 4-4 EEPROM Mapping ........................................................................................ 4-10 4-5 RAM and Register Mapping ...
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... Freescale Semiconductor, Inc. Table B-1 Device Ordering Information ........................................................................... B-3 C-1 MC68HC11F1 Development Tools .................................................................C-1 For More Information On This Product, LIST OF TABLES (Continued) Title Go to: www.freescale.com Page TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. SECTION 1INTRODUCTION The MC68HC11F1 high-performance microcontroller unit (MCU enhanced de- rivative of the M68HC11 family of microcontrollers and includes many advanced fea- tures. This MCU, with a nonmultiplexed expanded bus, is characterized by high speed and low power consumption. The fully static design allows operation at frequencies from 4 MHz to dc ...
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... Freescale Semiconductor, Inc. XTAL EXTAL E 4XOUT PULSE PA7 PAI/OC1 ACCUMULATOR PA6 OC2/OC1 PA5 OC3/OC1 PA4 OC4/OC1 PA3 OC5/IC4/OC1 PA2 IC1 PA1 IC2 PA0 IC3 PB7 ADDR15 PB6 ADDR14 PB5 ADDR13 PB4 ADDR12 PB3 ADDR11 PB2 ADDR10 PB1 ADDR9 PB0 ADDR8 PF7 ...
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... Freescale Semiconductor, Inc. SECTION 2 PIN DESCRIPTIONS The MC68HC11F1 MCU is available in a 68-pin plastic leaded chip carrier (PLCC) and an 80-pin plastic quad flat pack (QFP). Most pins on this MCU serve two or more func- tions, as described in the following paragraphs. Figure 2-1 shows the pin assignments for the PLCC ...
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... Freescale Semiconductor, Inc PB6/ADDR14 3 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PF7/ADDR7 10 PF6/ADDR6 11 PF5/ADDR5 12 PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 17 PE0/AN0 18 PE4/AN4 Figure 2-2 Pin Assignments for MC68HC11F1 80-Pin QFP 2 and SS Power is supplied to the MCU through ground. The MCU operates from a single 5-volt (nominal) power supply. Very SS fast signal transitions occur on the MCU pins ...
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... Freescale Semiconductor, Inc. 2.2 Reset (RESET ) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an inter- nal failure has been detected in either the clock monitor or COP watchdog circuit. The ...
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... Freescale Semiconductor, Inc. The XTAL pin is normally left unterminated when an external CMOS compatible clock is connected to the EXTAL pin. However from the XTAL output to ground can be used to reduce RFI noise emission. The XTAL output is normally used to drive a crystal. The XTAL output can be buffered with a high-impedance buffer can be used to drive the EXTAL input of another M68HC11 device ...
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... Freescale Semiconductor, Inc. 2.5 Four Times E-Clock Frequency Output (4XOUT) Although the circuit shown in Figure 2-6 will work for any M68HC11 MCU, the MC68HC11F1 has an additional clock output that is four times the E-clock frequency. This output (4XOUT) can be used to directly drive the EXTAL input of another M68HC11 MCU ...
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... Freescale Semiconductor, Inc. 2.8 MODA and MODB (MODA/LIR and MODB/V During reset, MODA and MODB select one of the four operating modes. Refer to SEC- TION 4 OPERATING MODES AND ON-CHIP MEMORY. After the operating mode has been selected, the LIR pin provides an open-drain output to indicate that execution of an instruction has begun ...
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... Freescale Semiconductor, Inc. Table 2-1 Port Signal Functions Port/Bit PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB[7:0] PC[7:0] PD0 PD1 PD2 PD3 PD4 PD5 PE[7:0] PF[7:0] PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 2.11.1 Port A Port 8-bit general-purpose I/O port with a data register (PORTA) and a data direction register (DDRA). Port A pins share functions with the 16-bit timer system. PORTA can be read at any time. Inputs return the pin level ...
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... Freescale Semiconductor, Inc. 2.11.2 Port B Port 8-bit output-only port. In single-chip modes, port B pins are general-pur- pose output pins (PB[7:0]). In expanded modes, port B pins act as the high-order ad- dress lines (ADDR[15:8]) of the address bus. PORTB can be read at any time. Reads of PORTB return the pin driver input level. If PORTB is written, the data is stored in internal latches ...
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... Freescale Semiconductor, Inc. OR mode, (PORTD bits are at logic level zero), pins are actively driven low by the N- channel driver. When a port D bit is at logic level one, the associated pin high- impedance state, as neither the N-channel nor the P-channel devices are active customary to have an external pull-up resistor on lines that are driven by open-drain devices ...
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... Freescale Semiconductor, Inc. 2-10 For More Information On This Product, PIN DESCRIPTIONS Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. SECTION 3 CENTRAL PROCESSING UNIT This section presents information on M68HC11 central processing unit (CPU) archi- tecture. Data types, addressing modes, the instruction set, and the extended address- ing range required to support this MCU’s memory expansion feature are also included, as are special operations such as subroutine calls and interrupts ...
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... Freescale Semiconductor, Inc. 15 DOUBLE ACCUMULATOR D 15 INDEX REGISTER X 15 INDEX REGISTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 3-1 Programming Model 3.1.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and re- sults of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumu- lator D ...
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... Freescale Semiconductor, Inc. The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and CBA) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. 3.1.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address ...
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... Freescale Semiconductor, Inc. JSR, JUMP TO SUBROUTINE MAIN PROGRAM PC $9D = JSR DIRECT dd RTN NEXT MAIN INSTR MAIN PROGRAM PC $AD = JSR INDXD,X ff RTN NEXT MAIN INSTR MAIN PROGRAM PC $18 = PRE $AD = JSR INDXD,Y ff RTN NEXT MAIN INSTR MAIN PROGRAM PC $BD = JSR hh EXTEND ll RTN NEXT MAIN INSTR ...
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... Freescale Semiconductor, Inc. When an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. At the end of the interrupt service routine, an RTI instruction is executed ...
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... Freescale Semiconductor, Inc. 3.1.6.3 Zero (Z) The Z bit is set if the result of an arithmetic, logic, or data manipulation operation is zero. Otherwise, the Z bit is cleared. Compare instructions do an internal implied sub- traction and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags. ...
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... Freescale Semiconductor, Inc. 3.1.6.8 Stop Disable (S) Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 into a low-power stop condition. If the CPU encounters a STOP instruction while the S bit is set treated as a no-operation (NOP) instruction, and processing continues to the next instruction set by reset — STOP disabled by default. ...
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... Freescale Semiconductor, Inc. (if prebyte is required) byte immediate instructions. The effective address is the ad- dress of the byte following the instruction. 3.4.2 Direct In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is as- sumed to be $00. Addresses $00– ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description ABA Add Accumulators ABX Add ( ABY Add ( ADCA (opr) Add with Carry ADCB (opr) Add with Carry ADDA (opr) Add Memory ADDB (opr) Add Memory ADDD (opr) Add 16-Bit ANDA (opr) AND A with A • ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description BGT (rel) Branch if > Zero BHI (rel) Branch Higher BHS (rel) Branch Higher or Same BITA (opr) Bit(s) Test A A • M with Memory BITB (opr) Bit(s) Test B B • M with Memory ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description COM (opr) Ones $FF – Complement Memory Byte COMA Ones $FF – Complement A COMB Ones $FF – Complement B CPD (opr) Compare – Memory 16-Bit CPX (opr) Compare – Memory 16-Bit CPY (opr) Compare – ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description INY Increment Index Register Y JMP (opr) Jump See Figure 3–2 JSR (opr) Jump to See Figure 3–2 Subroutine LDAA (opr) Load M A Accumulator A LDAB (opr) Load M B Accumulator B LDD (opr) Load Double ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description NOP No operation No Operation ORAA (opr Accumulator A (Inclusive) ORAB (opr Accumulator B (Inclusive) PSHA Push A onto A Stk, – Stack PSHB Push B onto B Stk, – Stack PSHX Push X onto IX Stk, – 2 Stack (Lo First) ...
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... Freescale Semiconductor, Inc. Table 3-2 Instruction Set (Sheet Mnemonic Operation Description STAB (opr) Store B M Accumulator B STD (opr) Store Accumulator D STOP Stop Internal — Clocks STS (opr) Store Stack Pointer STX (opr) Store Index Register X STY (opr) Store Index Register Y SUBA (opr) Subtract A – ...
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... Freescale Semiconductor, Inc. SECTION 4OPERATING MODES AND ON-CHIP MEMORY This section contains information about the modes that define MC68HC11F1 operat- ing conditions, and about the on-chip memory that allows the MCU to be configured for various applications. 4.1 Operating Modes The values of the mode select inputs MODB and MODA during reset determine the operating mode ...
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... Freescale Semiconductor, Inc. The bootstrap ROM contains a small program which initializes the SCI and allows the user to download a program 1024 bytes into on-chip RAM. After a four-char- acter delay, or after receiving the character for address $03FF, control passes to the loaded program at $0000. An external pull-up resistor is required when using the SCI transmitter pin (TxD) because port D pins are configured for wired-OR operation by the bootloader ...
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... Freescale Semiconductor, Inc. 4.2.2 Memory Map $0000 EXT $1000 EXT $FE00 $FFFF SINGLE EXPANDED BOOTSTRAP CHIP NOTES: 1. RAM can be remapped to any 4-Kbyte boundary ($x000). "x" represents the value contained in RAM[3:0] in the init register. 2. The register block can be remapped to any 4-Kbyte boundary ($y000). "y" represents the value contained in reg[3:0] in the init register ...
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... Freescale Semiconductor, Inc. During the software-based STOP mode, MCU clocks are stopped, but the MCU con- tinues to draw power from V ating frequency in CMOS integrated circuits and there is very little leakage when the clocks are stopped. These two factors reduce power consumption while the MCU is in STOP mode ...
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... Freescale Semiconductor, Inc. Table 4-1 Register and Control Bit Assignments The register block can be remapped to any 4-Kbyte boundary. Bit $1000 PA7 PA6 PA5 $1001 DDA7 DDA6 DDA5 $1002 PG7 PG6 PG5 $1003 DDG7 DDG6 DDG5 $1004 PB7 PB6 PB5 $1005 PF7 ...
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... Freescale Semiconductor, Inc. Table 4-1 Register and Control Bit Assignments (Continued) The register block can be remapped to any 4-Kbyte boundary. Bit $1028 SPIE SPE DWOM $1029 SPIF WCOL 0 $102A Bit $102B TCLR 0 SCP1 $102C $102D TIE TCIE RIE $102E TDRE TC RDRF $102F ...
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... Freescale Semiconductor, Inc. Table 4-2 Write Access Limited Registers Register Address $x024 Timer Interrupt Mask 2 (TMSK2) $x035 Block Protect Register (BPROT) $x038 System Configuration Options 2 (OPT2) $x039 System Configuration Options (OPTION) $x03C Highest Priority I-bit and Miscellaneous (HPRIO) $x03D RAM and I/O Map Register (INIT) Notes: 1 ...
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... Freescale Semiconductor, Inc. A normal mode is selected when MODB is logic one during reset. One of three reset vectors is fetched from address $FFFA–$FFFF, and program execution begins from the address indicated by this vector. If MODB is logic zero during reset, the special mode reset vector is fetched from addresses $BFFA–$BFFF and software has access to special test features ...
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... Freescale Semiconductor, Inc. 4.3.2 Initialization Because bits in the following registers control the basic configuration of the MCU, an accidental change of their values could cause serious system problems. The protec- tion mechanism, overridden in special operating modes, requires a write to the protect- ed bits only within the first 64 bus cycles after any reset, or only once after each reset. ...
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... Freescale Semiconductor, Inc. Table 4-4 EEPROM Mapping EE[3: Bit 3 — Not implemented Always reads one NOCOP — COP System Disable 0 = COP system enabled (forces reset on time-out COP system disabled Bit 1 — Not implemented Always reads one EEON — EEPROM Enable In single-chip modes EEON is forced to one (EEPROM enabled). ...
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... Freescale Semiconductor, Inc. RAM[3:0] — RAM Map Position These four bits, which specify the upper hexadecimal digit of the RAM address, control position of RAM in the memory map. RAM can be positioned at the beginning of any 4-Kbyte page in the memory map. Refer to Table 4-5. REG[3:0] — 128-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 128-byte block of internal registers ...
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... Freescale Semiconductor, Inc. ADPU — A/D Power-Up Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER A/D system disabled 1 = A/D system power enabled CSEL — Clock Select Selects alternate clock source for on-chip EEPROM and A/D charge pumps. On-chip RC clock should be used when E clock falls below 1 MHz. Refer to SECTION 10 AN- ALOG-TO-DIGITAL CONVERTER ...
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... Freescale Semiconductor, Inc. OPT2 — System Configuration Options 2 Bit 7 6 GWOM CWOM CLK4X RESET GWOM — Port G Wired-OR Mode Refer to SECTION 6 PARALLEL INPUT/OUTPUT Port G operates normally Port G outputs are open-drain type. CWOM — Port C Wired-OR Mode Refer to SECTION 6 PARALLEL INPUT/OUTPUT Port C operates normally. ...
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... Freescale Semiconductor, Inc. Table 4-6 EEPROM Block Protection Bit Name BPRT0 BPRT1 BPRT2 BPRT3 4.4 EEPROM and CONFIG Register The 512-byte EEPROM array and the single-byte CONFIG register are implemented with the same type of memory cells. The CONFIG register is a separate address lo- cated within the register block rather than in the EEPROM array ...
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... Freescale Semiconductor, Inc. Recall that zeros must be erased by a separate erase operation before programming. The following example of how to program an EEPROM byte assumes that the appro- priate bits in BPROT have been cleared and the data to be programmed is present in accumulator A. PROG LDAB #$02 STAB ...
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... Freescale Semiconductor, Inc. ROWE LDAB #$0E STAB $103B STAB 0,X LDAB #$0F STAB $103B JSR DLY10 CLR $103B 4.4.1.4 EEPROM Byte Erase The following is an example of how to erase a single byte of EEPROM and assumes that index register X contains the address of the byte to be erased. ...
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... Freescale Semiconductor, Inc. Table 4-7 EEPROM Erase Mode Control BYTE ERASE — Erase/Normal Control for EEPROM Can be read or written any time Normal read or program mode 1 = Erase mode EELAT — EEPROM Latch Control Can be read or written any time. When EELAT equals one, writes to EEPROM cause address and data to be latched ...
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... Freescale Semiconductor, Inc. For a description of the bits contained in the CONFIG register refer to 4.3.2.1 CONFIG Register. 4.5 Chip Selects The function of the chip selects is to minimize the amount of external glue logic needed to interface the MCU to external devices. The MC68HC11F1 has four software config- ured chip selects that can be enabled in expanded modes ...
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... Freescale Semiconductor, Inc. $0000 $1000 x000 96-BYTE REGISTER x05F BLOCK $8000 x060 I/O CHIP SELECT 1 (CSIO1) x7FF x800 I/O CHIP SELECT 2 (CSIO2) xFFF $C000 $E000 $FE00 $FFFF EXPANDED MODE Figure 4-3 Address Map for I/O and Program Chip Selects 4.5.3 General-Purpose Chip Select The general-purpose chip select (CSGEN) is the most flexible and has the most con- trol bits ...
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... Freescale Semiconductor, Inc. $0000 EXP MODE ADDR SPACE $FFFF VALID BASE ADDR BITS: N/A GA15 GSIZA : GSIZB : GSIZC 64K SIZE: Figure 4-4 Address Map for General-Purpose Chip Select CSSTRH — Chip Select Clock Stretch Select Bit 7 6 IO1SA IO1SB IO2SA RESET: ...
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... Freescale Semiconductor, Inc. CSCTL — Chip Select Control Bit 7 6 IO1EN IO1PL IO2EN RESET *PCSEN is set out of reset in expanded modes and cleared in single-chip modes. IO1EN — I/O Chip Select 1 Enable 0 = CSIO1 is disabled and port G bit 5 is general-purpose I/ CSIO1 is enabled and uses port G bit 5. ...
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... Freescale Semiconductor, Inc. Table 4-10 General-Purpose Chip Select Starting Address 0 K (Disabled) CSGSIZ — General-Purpose Chip Select Size Control Bit 7 6 IO1AV IO2AV RESET IO1AV — I/O Chip Select 1 Address Valid 0 = I/O chip select 1 is active during E-clock valid time (E-clock high I/O chip select 1 is active during address valid time IO2AV — ...
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... Freescale Semiconductor, Inc. Table 4-12 Chip Select Control Parameter Summary CSIO1 Enable Valid Polarity Size Start Address Stretch CSIO2 Enable Valid Polarity Size Start Address Stretch CSPROG Enable Valid Polarity Size Start Address Stretch Priority CSGEN Enable Valid Polarity Size Start Address ...
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... Freescale Semiconductor, Inc. OPERATING MODES AND ON-CHIP MEMORY 4-24 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. SECTION 5 RESETS AND INTERRUPTS Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset causes the internal control registers to be initialized to a known state. The program counter is loaded with a known starting address and execution of instructions begins ...
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... Freescale Semiconductor, Inc. 5.1.3 Computer Operating Properly (COP) Reset The MCU includes a COP system to help protect against software failures. When the COP is enabled, the software is responsible for keeping a free-running watchdog timer from timing out. When the software is no longer being executed in the intended se- quence, a system reset is initiated ...
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... Freescale Semiconductor, Inc. Semiconductor wafer processing causes variations of the RC time-out values between individual devices. An E-clock frequency below 10 kHz is detected as a clock monitor error. An E-clock frequency of 200 kHz or more prevents clock monitor errors. Using the clock monitor function when the E-clock is below 200 kHz is not recommended. ...
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... Freescale Semiconductor, Inc. CR[1:0] — COP Timer Rate Select The internal E clock is first divided by 2 These control bits determine a scaling factor for the watchdog timer. Refer to Table 5- 1. 5.1.6 CONFIG Register CONFIG — System Configuration Register Bit 7 6 EE3 EE2 EE1 ...
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... Freescale Semiconductor, Inc. 5.2.1 Central Processing Unit After reset, the CPU fetches the reset vector from the appropriate address during the first three cycles, and begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition code register (CCR) are set to mask any interrupt requests ...
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... Freescale Semiconductor, Inc. 5.2.6 Pulse Accumulator The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin defaults to being a general-purpose input pin. 5.2.7 Computer Operating Properly (COP) The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis- ter is cleared, and disabled if NOCOP is set ...
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... Freescale Semiconductor, Inc. 1. POR or RESET pin 2. Clock monitor reset 3. COP watchdog reset 4. XIRQ interrupt 5. Illegal opcode interrupt 6. Software interrupt (SWI) The maskable interrupt sources have the following priority arrangement: 1. IRQ 2. Real-time interrupt 3. Timer input capture 1 4. Timer input capture 2 5. Timer input capture 3 6 ...
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... Freescale Semiconductor, Inc. SMOD — Special Mode Select Can be read any time. Can only be written in special modes (SMOD = 1). Can only be written to zero. Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information. MDA — Mode Select A Can be read any time. Can only be written in special modes (SMOD = 1). Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY for more information. IRV — ...
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... Freescale Semiconductor, Inc. Table 5-4 Interrupt and Reset Vector Assignments Vector Address FFC0, C1 – FFD4, D5 FFD6, D7 FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests ...
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... Freescale Semiconductor, Inc. at the address specified by the vector. At the end of the interrupt service routine, the return from interrupt instruction is executed and the saved registers are pulled from the stack in reverse order so that normal program execution can resume. Refer to SEC- TION 3 CENTRAL PROCESSING UNIT for further information. ...
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... Freescale Semiconductor, Inc. The illegal opcode trap mechanism works for all unimplemented opcodes on all four opcode map pages. The address stacked as the return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. ...
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... Freescale Semiconductor, Inc. HIGHEST POWER-ON RESET (POR) EXTERNAL RESET DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, FFFF (VECTOR FETCH) 1A YES Figure 5-1 Processing Flow Out of Reset ( 5-12 For More Information On This Product, PRIORITY CLOCK MONITOR FAIL (WITH CME = 1) LOAD PROGRAM COUNTER ...
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... Freescale Semiconductor, Inc. STACK CPU REGISTERS SET X AND I BITS FETCH VECTOR $FFE8, FFE9 STACK CPU REGISTERS SET X AND I BITS FETCH VECTOR $FFE6, FFE7 RESTORE CPU REGISTERS FROM STACK Figure 5-2 Processing Flow Out of Reset ( TECHNICAL DATA For More Information On This Product, ...
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... Freescale Semiconductor, Inc. BEGIN X BIT YES IN CCR SET ? NO HIGHEST YES PRIORITY INTERRUPT ? NO YES IRQ ? NO YES RTII = YES IC1I = YES IC2I = YES IC3I = YES OC1I = Figure 5-3 Interrupt Priority Resolution ( 5-14 For More Information On This Product, XIRQ PIN YES SET X BIT IN CCR ...
Page 77
... Freescale Semiconductor, Inc. 2A YES OC2I = YES OC3I = YES OC4I = YES OC5/IC4I = YES TOI = YES PAOVI = YES PAII = YES SPIE = SCI YES (REFER TO FIG 5-3) ? SPURIOUS INTERRUPT – TAKE IRQ VECTOR NO Figure 5-4 Interrupt Priority Resolution ( TECHNICAL DATA For More Information On This Product, ...
Page 78
... Freescale Semiconductor, Inc. BEGIN YES RDRF = YES YES TDRE = YES YES IDLE = – VALID SCI REQUEST Figure 5-5 Interrupt Source Resolution Within SCI 5.5 Low Power Operation Both STOP and WAIT suspend CPU operation until a reset or interrupt occurs. The WAIT condition suspends processing and reduces power consumption to an interme- diate level ...
Page 79
... Freescale Semiconductor, Inc. 5.5.1 WAIT The WAI opcode places the MCU in the WAIT condition, during which the CPU regis- ters are stacked and CPU processing is suspended until a qualified interrupt is detect- ed. The interrupt can be an external IRQ, an XIRQ, or any of the internally generated interrupts, such as the timer or serial interrupts ...
Page 80
... Freescale Semiconductor, Inc. Because the oscillator is stopped in STOP mode, a restart delay may be imposed to allow oscillator stabilization upon leaving STOP. If the internal oscillator is being used, this delay is required; however stable external oscillator is being used, the DLY control bit can be used to bypass this start-up delay. The DLY control bit is set by reset and can be optionally cleared during initialization ...
Page 81
... Freescale Semiconductor, Inc. SECTION 6 PARALLEL INPUT/OUTPUT The MC68HC11F1 MCU has input/output lines, depending on the operating mode. The data bus of this microcontroller is nonmultiplexed. I/O lines are organized into seven parallel ports. Ports with bidirectional pins have an associated data direc- tion control register. This register (DDRx) contains a data direction control bit for each bidirectional port line ...
Page 82
... Freescale Semiconductor, Inc. DDRA — Data Direction Register for Port A Bit 7 6 DDA7 DDA6 DDA5 RESET DDA[7:0] — Data Direction for Port Input 1 = Output To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared ...
Page 83
... Freescale Semiconductor, Inc. impedance state, as neither the N-channel nor the P-channel devices are active customary to have an external pull-up resistor on lines that are driven by open-drain devices. Port C can only be configured for wired-OR operation when the MCU is in sin- gle-chip or bootstrap modes. PORTC — Port C Data ...
Page 84
... Freescale Semiconductor, Inc. DDRD — Data Direction Register for Port D Bit 7 6 — — DDD5 RESET Bits [7:6] — Not implemented Always read zero DDD[5:0] — Data Direction for Port Input 1 = Output When the SPI system is in slave mode, DDD5 has no meaning nor effect ...
Page 85
... Freescale Semiconductor, Inc. PORTF — Port F Data Bit 7 6 PF7 PF6 S. Chip or Boot: PF7 PF6 RESET Expan. or Test: ADDR7 ADDR6 ADDR5 6.7 Port G Port G pins reset to high-impedance inputs except in expanded modes where reset causes PG7 to become the CSPROG output. Alternate functions for port G bits [7:4] are chip select outputs ...
Page 86
... Freescale Semiconductor, Inc. OPT2 — System Configuration Options 2 Bit 7 6 GWOM CWOM CLK4X RESET GWOM — Port G Wired-OR Mode 0 = Port G operates normally 1 = Port G outputs are open drain CWOM — Port C Wired-OR Mode 0 = Port C operates normally 1 = Port C outputs are open drain CLK4X — 4XOUT Clock Enable Refer to SECTION 2 PIN DESCRIPTIONS. Bits [4:0] — ...
Page 87
... Freescale Semiconductor, Inc. SECTION 7 SERIAL COMMUNICATIONS INTERFACE The serial communications interface (SCI universal asynchronous receiver trans- mitter (UART), one of two independent serial I/O subsystems in the MC68HC11F1 MCU. It has a standard nonreturn to zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit). Several baud rates are available. The SCI transmitter and re- ceiver are independent, but use the same data format and bit rate ...
Page 88
... Freescale Semiconductor, Inc. TRANSMITTER SCDR Tx BUFFER BAUD RATE CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 7-1 SCI Transmitter Block Diagram 7.3 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word ...
Page 89
... Freescale Semiconductor, Inc. RECEIVER BAUD RATE CLOCK DDD0 PIN BUFFER PD0/ AND CONTROL RxD DISABLE DRIVER WAKE-UP LOGIC SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 7-2 SCI Receiver Block Diagram SERIAL COMMUNICATIONS INTERFACE TECHNICAL DATA For More Information On This Product, ...
Page 90
... Freescale Semiconductor, Inc. 7.4 Wakeup Feature The wakeup feature reduces SCI service overhead in multiple receiver systems. Soft- ware for each receiver evaluates the first character of each message. The receiver is placed in wakeup mode by writing a one to the RWU bit in the SCCR2 register. While RWU is one, all of the receiver-related status flags (RDRF, IDLE, OR, NF, and FE) are inhibited (cannot become set) ...
Page 91
... Freescale Semiconductor, Inc. 7.5 SCI Error Detection Three error conditions, SCDR overrun, received bit noise, and framing can occur dur- ing generation of SCI system interrupts. Three bits (OR, NF, and FE) in the serial com- munications status register (SCSR) indicate if one of these error conditions exists. ...
Page 92
... Freescale Semiconductor, Inc. R8 — Receive Data Bit bit is set, R8 stores the ninth bit in the receive data character. T8 — Transmit Data Bit bit is set, T8 stores the ninth bit in the transmit data character. M — Mode (Select Character Format Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE — ...
Page 93
... Freescale Semiconductor, Inc. RWU — Receiver Wakeup Control 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK — Send Break At least one character time of break is queued and sent each time SBK is written to one. As long as the SBK bit is set, break characters are queued and sent. More than ...
Page 94
... Freescale Semiconductor, Inc. OR — Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR and then reading SCDR overrun 1 = Overrun detected NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. ...
Page 95
... Freescale Semiconductor, Inc. RCKB — SCI Baud Rate Clock Check (Test) SCR[2:0] — SCI Baud Rate Selects Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to the SCI baud rate generator block diagram. Table 7-2 Baud Rate Selection ...
Page 96
... Freescale Semiconductor, Inc. EXTAL OSCILLATOR AND CLOCK GENERATOR ( 4) XTAL Figure 7-3 SCI Baud Rate Generator Block Diagram 7.7 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present ...
Page 97
... Freescale Semiconductor, Inc. TDRE and TC flags are normally set when the transmitter is first enabled (TE set to one). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE is zero, TDRE must be polled ...
Page 98
... Freescale Semiconductor, Inc. BEGIN YES RDRF = YES YES TDRE = YES YES IDLE = – VALID SCI REQUEST Figure 7-4 Interrupt Source Resolution Within SCI SERIAL COMMUNICATIONS INTERFACE 7-12 For More Information On This Product, YES RIE = YES TIE = YES TCIE = YES ILIE = to: www.freescale.com ...
Page 99
... Freescale Semiconductor, Inc. SECTION 8 SERIAL PERIPHERAL INTERFACE The serial peripheral interface (SPI), an independent serial communications sub- system, allows the MCU to communicate synchronously with peripheral devices, such as transistor-transistor logic (TTL) shift registers, liquid crystal display (LCD) drivers, analog-to-digital converter subsystems, and other microprocessors. The SPI is also capable of inter-processor communication in a multiple master system ...
Page 100
... Freescale Semiconductor, Inc. INTERNAL MCU CLOCK DIVIDER SPI CLOCK (MASTER) SELECT SPI CONTROL SPSR SPI STATUS REGISTER SPI INTERRUPT REQUEST Figure 8-1 SPI Block Diagram 8.2 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. ...
Page 101
... Freescale Semiconductor, Inc. SCK CYCLE # 1 SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT MSB SAMPLE INPUT (CPHA = 1) DATA OUT MSB SS (TO SLAVE ASSERTED MASTER WRITES SPDR 3 FIRST SCK EDGE 4 SPIF SET 5 SS NEGATED Figure 8-2 SPI Transfer Format 8.2.1 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR) ...
Page 102
... Freescale Semiconductor, Inc. 8.3.1 Master In Slave Out MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. 8.3.2 Master Out Slave In The MOSI line is the second of the two unidirectional serial data signals ...
Page 103
... Freescale Semiconductor, Inc. When the SPI system is configured as a master and the SS input line goes to active low, a mode fault error has occurred — usually because two devices have attempted to act as master at the same time. In cases where more than one device is concurrent- ly configured as a master, there is a chance of contention between two pin drivers ...
Page 104
... Freescale Semiconductor, Inc. SPIE — Serial Peripheral Interrupt Enable Set the SPE bit to one to request a hardware interrupt sequence each time the SPIF or MODF status flag is set. SPI interrupts are inhibited if this bit is clear or if the I bit in the condition code register is one. ...
Page 105
... Freescale Semiconductor, Inc. 8.5.2 Serial Peripheral Status SPSR — Serial Peripheral Status Register Bit 7 6 SPIF WCOL RESET SPIF — SPI Interrupt Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. ...
Page 106
... Freescale Semiconductor, Inc. SERIAL PERIPHERAL INTERFACE 8-8 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
Page 107
... Freescale Semiconductor, Inc. SECTION 9 TIMING SYSTEM The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programma- ble prescaler. The main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale rate ...
Page 108
... Freescale Semiconductor, Inc. OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER ( 2, 4, 16, 32) SPR[1:0] PRESCALER ( 13) SCP[1: PRESCALER ( 16) PR[1:0] TCNT IC/OC Figure 9-1 Timer Clock Divider Chains 9-2 For More Information On This Product, PRESCALER ( 1, 2, 4,....128) SCR[2:0] 16 PRESCALER ( RTR[1: PRESCALER ( 1, 4, 16, 64) CR[1:0] ...
Page 109
... Freescale Semiconductor, Inc. 4.0 MHz 1.0 MHz Control Bits 1000 ns PR1, PR0 count — 1.0 s overflow — 65.536 count — 4.0 s overflow — 262. count — 8.0 s overflow — 524. count — 16.0 s overflow — 1.049 s 9.1 Timer Structure Figure 9-2 shows the capture/compare system block diagram. The port A pin control block includes logic for timer functions and for general-purpose I/O ...
Page 110
... Freescale Semiconductor, Inc. PRESCALER–DIVIDE BY MCU ECLK PR1 PR0 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 16-BIT LATCH CLK TIC1 (HI) ...
Page 111
... Freescale Semiconductor, Inc. 9.2 Input Capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched values and use them to compute the peri- odicity and duration of events ...
Page 112
... Freescale Semiconductor, Inc. 9.2.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel trans- fer. Timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase 2 clock so that the count value is stable whenever a capture occurs ...
Page 113
... Freescale Semiconductor, Inc. To produce a pulse of a specific duration, write a value to the output compare register that represents the time the leading edge of the pulse is to occur. The output compare circuit is configured to set the appropriate output either high or low, depending on the polarity of the pulse being produced. After a match occurs, the output compare register is reprogrammed to change the output pin back to its inactive level at the next match ...
Page 114
... Freescale Semiconductor, Inc. TOC1–TOC4 — Timer Output Compare $1016 Bit $1017 Bit $1018 Bit $1019 Bit $101A Bit $101B Bit $101C Bit $101D Bit All TOCx register pairs reset to ones ($FFFF). 9.3.2 Timer Compare Force Register The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares ...
Page 115
... Freescale Semiconductor, Inc. OC1M — Output Compare 1 Mask Bit 7 6 OC1M7 OC1M6 OC1M5 RESET OC1M[7:3] — Output Compare Masks 0 = OC1 is disabled OC1 is enabled to control the corresponding pin of port A Bits [2:0] — Not implemented Always read zero 9.3.4 Output Compare Data Register Use this register with OC1 to specify the data that stored on the affected pin of port A after a successful OC1 compare ...
Page 116
... Freescale Semiconductor, Inc. TCTL1 — Timer Control 1 Bit 7 6 OM2 OL2 RESET OM[2:5] — Output Mode OL[2:5] — Output Level These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to Table 9-3 for the coding ...
Page 117
... Freescale Semiconductor, Inc. 9.3.8 Timer Interrupt Flag Register 1 Bits in this register indicate when timer system events have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position. TFLG1 — ...
Page 118
... Freescale Semiconductor, Inc. Table 9-3 Timer Prescaler Selection PR[1:0] Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. 9.3.10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system ...
Page 119
... Freescale Semiconductor, Inc. Table 9-4 RTI Rate Selection RTR[1: MHz 0 0 8.192 16.384 32.768 65.536 ms The clock source for the RTI function is a free-running clock that cannot be stopped or interrupted except by reset. This clock causes the time between successive RTI time- outs constant that is independent of the software latencies associated with flag clearing and service ...
Page 120
... Freescale Semiconductor, Inc. 9.4.2 Timer Interrupt Flag Register 2 Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position. TFLG2 — ...
Page 121
... Freescale Semiconductor, Inc. PEDGE — Pulse Accumulator Edge Control Refer to 9.6 Pulse Accumulator. Bit 3 — Not implemented Always reads zero I4/O5 — Input Capture 4/Output Compare Refer to 9.6 Pulse Accumulator. RTR[1:0] — RTI Interrupt Rate Select These two bits determine the rate at which the RTI system requests interrupts. The RTI system is driven divided by 2 dependent of the timer prescaler ...
Page 122
... Freescale Semiconductor, Inc CLOCK (FROM MAIN TIMER) TMSK2 INT ENABLES PIN PA7/ INPUT BUFFER PAI/ AND OC1 EDGE DETECTOR OUTPUT BUFFER FROM MAIN TIMER OC1 FROM DATA DIRECTION PACTL CONTROL BIT FOR PORT A PIN 7 Figure 9-3 Pulse Accumulator Table 9-5 Pulse Accumulator Timing ...
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... Freescale Semiconductor, Inc. PACTL — Pulse Accumulator Control Bit 7 6 — PAEN PAMOD RESET Bit 7 — Not implemented Always reads zero PAEN — Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD — Pulse Accumulator Mode 0 = Event counter 1 = Gated time accumulation PEDGE — ...
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... Freescale Semiconductor, Inc. 9.6.3 Pulse Accumulator Status and Interrupt Bits The pulse accumulator control bits, PAOVI, PAII, PAOVF, and PAIF are located within timer registers TMSK2 and TFLG2. TMSK2 — Timer Interrupt Mask 2 Register Bit 7 6 TOI RTII PAOVI RESET TFLG2 — Timer Interrupt Flag 2 Register ...
Page 125
... Freescale Semiconductor, Inc. SECTION 10 ANALOG-TO-DIGITAL CONVERTER The analog-to-digital (A/D) system, a successive approximation converter, uses an all- capacitive charge redistribution technique to convert analog signals to digital values. 10.1 Overview The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The AV used to input supply voltage to the A/D converter. This allows the supply voltage to be bypassed independently ...
Page 126
... Freescale Semiconductor, Inc. PE0/ AN0 PE1/ AN1 PE2/ AN2 PE3/ RESULT AN3 ANALOG MUX PE4/ AN4 PE5/ AN5 PE6/ AN6 PE7/ AN7 ADDR 1 A/D RESULT 1 Figure 10-1 A/D Converter Block Diagram Port E pins can also be used as digital inputs. Reads of port E pins are not recom- mended during the sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on ...
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... Freescale Semiconductor, Inc. INPUT PROTECTION DEVICE ANALOG INPUT PIN < This analog switch is closed only during the 12-cycle sample time. Figure 10-2 Electrical Model of an A/D Input Pin (Sample Mode) 10.1.2 Analog Converter Conversion of an analog input selected by the multiplexer occurs in this block. It con- tains a digital-to-analog capacitor (DAC) array, a comparator, and a successive ap- proximation register (SAR) ...
Page 128
... Freescale Semiconductor, Inc. indicates when valid data is present in the result registers. The result registers are writ- ten during a portion of the system clock cycle when reads do not occur, so there is no conflict. 10.1.5 A/D Converter Clocks The CSEL bit in the OPTION register selects whether the A/D converter uses the sys- tem E clock or an internal RC oscillator for synchronization ...
Page 129
... Freescale Semiconductor, Inc. 10.2 A/D Converter Power-Up and Clock Select Bit 7 of the OPTION register controls A/D converter power up. Clearing ADPU re- moves power from and disables the A/D converter system. Setting ADPU enables the A/D converter system. Stabilization of the analog bias voltages requires a delay of as much as 100 s after turning on the A/D converter ...
Page 130
... Freescale Semiconductor, Inc. 10.4 Channel Assignments The multiplexer allows the A/D converter to select one of sixteen analog signals. Eight of these channels correspond to port E input lines, four of the channels are internal reference points or test functions, and four channels are reserved. Refer to Table 10- 1 ...
Page 131
... Freescale Semiconductor, Inc. 10.7 Operation in STOP and WAIT Modes If a conversion sequence is in progress when either the STOP or WAIT mode is en- tered, the conversion of the current channel is suspended. When the MCU resumes normal operation, that channel is resampled and the conversion sequence is resumed. ...
Page 132
... Freescale Semiconductor, Inc. When the multiple-channel continuous scan mode is used, extra care is needed in the design of circuitry driving the A/D inputs. The charge on the capacitive DAC array before the sample time is related to the voltage on the previously converted channel. A charge share situa- tion exists between the internal DAC capacitance and the external circuit capacitance ...
Page 133
... Freescale Semiconductor, Inc. ADR1–ADR4 — A/D Results $1031 Bit 7 6 $1032 Bit 7 6 $1033 Bit 7 6 $1034 Bit 7 6 ANALOG-TO-DIGITAL CONVERTER TECHNICAL DATA For More Information On This Product to: www.freescale.com $1031–$1034 1 Bit 0 ADR1 1 Bit 0 ADR2 1 Bit 0 ADR3 1 Bit 0 ADR4 ...
Page 134
... Freescale Semiconductor, Inc. ANALOG-TO-DIGITAL CONVERTER 10-10 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
Page 135
... Freescale Semiconductor, Inc. APPENDIX A ELECTRICAL CHARACTERISTICS This appendix contains electrical parameters for the MC68HC11F1 microcontroller. Table A-1 Maximum Ratings Rating Supply Voltage Input Voltage Operating Temperature Range MC68HC11F1 MC68HC11F1C MC68HC11F1V MC68HC11F1M Storage Temperature Range Current Drain per Pin* Excluding and V DD ...
Page 136
... Freescale Semiconductor, Inc. Table A-2 Thermal Characteristics Characteristic Average Junction Temperature Ambient Temperature Package Thermal Resistance (Junction-to-Ambient) 68-Pin Plastic Leaded Chip Carrier 80-Pin Low Profile Quad Flat Pack (LQFP, 1.4 mm Thick) Total Power Dissipation Device Internal Power Dissipation I/O Pin Power Dissipation ...
Page 137
... Freescale Semiconductor, Inc. Table A-3 DC Electrical Characteristics V = 5.0 Vdc DD Characteristic Output Voltage (Note 1) All Outputs Except XTAL, RESET, and MODA I = 10.0 A Load Output High Voltage (Note 1) All Outputs Except XTAL, RESET, and MODA I = – 0.8 mA 4.5 V Load DD Output Low Voltage All Outputs Except XTAL ...
Page 138
... Freescale Semiconductor, Inc CLOCKS/ STROBES 0.4 V INPUTS ~V DD OUTPUTS ~ TESTING ~V DD CLOCKS/ 20 STROBES INPUTS ~V DD OUTPUTS ~ TESTING NOTES: 1. Full test loads are applied during all DC electrical tests and AC timing measurements. 2. During AC timing measurements, inputs are driven to 0.4 volts and V taken at the 20% and 70 points. ...
Page 139
... Freescale Semiconductor, Inc Characteristic Frequency of Operation E-Clock Period Crystal Frequency External Oscillator Frequency Processor Control Setup Time t = 1/4 t PCSU Reset Input Pulse Width (Notes 2, 3) (To Guarantee External Reset Vector) (Minimum Input Time; Can Be Preempted by Internal Reset) Mode Programming Setup Time Mode Programming Hold Time ...
Page 140
... Freescale Semiconductor, Inc. Figure A-3 POR External Reset Timing Diagram ELECTRICAL CHARACTERISTICS A-6 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
Page 141
... Freescale Semiconductor, Inc. Figure A-4 STOP Recovery Timing Diagram ELECTRICAL CHARACTERISTICS TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com A-7 ...
Page 142
... Freescale Semiconductor, Inc. Figure A-5 WAIT Recovery from Interrupt Timing Diagram ELECTRICAL CHARACTERISTICS A-8 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. Figure A-6 Interrupt Timing Diagram ELECTRICAL CHARACTERISTICS TECHNICAL DATA For More Information On This Product, Go to: www.freescale.com A-9 ...
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... Freescale Semiconductor, Inc. Table A-5 Peripheral Port Timing V DD Characteristic Frequency of Operation (E-Clock Frequency) E-Clock Period Peripheral Data Setup Time (MCU Read of Ports Peripheral Data Hold Time (MCU Read of Ports Delay Time, Peripheral Data Write (MCU Write to Port A) (MCU Write to Ports and G ...
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... Freescale Semiconductor, Inc. Table A-6 Analog-To-Digital Converter Characteristics V = 5.0 Vdc 5 Characteristic Parameter Resolution Number of Bits Resolved by A/D Converter Non-Linearity Maximum Deviation from the Ideal A/D Transfer Characteristics Zero Error Difference Between the Output of an Ideal and an Actual for Zero Input Voltage ...
Page 146
... Freescale Semiconductor, Inc. Table A-7 Expansion Bus Timing V DD Num Characteristic Frequency of Operation (E-Clock Frequency) 1 Cycle Time 2 Pulse Width, E Low PW = 1/2 t – cyc 3 Pulse Width, E High PW = 1/2 t – cyc 4A E Clock 4B 9 Address Hold Time t = 1/8 t – cyc 11 Address Delay Time ...
Page 147
... Freescale Semiconductor, Inc R/W, ADDRESS READ DATA WRITE DATA CS E VALID CS AD VALID 54 Figure A-9 Expansion Bus Timing ELECTRICAL CHARACTERISTICS TECHNICAL DATA For More Information On This Product to: www.freescale.com A-13 ...
Page 148
... Freescale Semiconductor, Inc. Table A-8 Serial Peripheral Interface Timing V DD Num Characteristic Operating Frequency Master Slave 1 Cycle Time Master Slave 2 Enable Lead Time Master Slave 3 Enable Lag Time Master Slave 4 Clock (SCK) High Time Master Slave 5 Clock (SCK) Low Time Master ...
Page 149
... Freescale Semiconductor, Inc HELD HIGH ON MASTER (INPUT) SCK (CPOL = 0) SEE NOTE (OUTPUT) SCK (CPOL = 1) SEE NOTE (OUTPUT) MISO (INPUT) 10 (ref) MOSI (OUTPUT) NOTE: This first clock edge is generated internally but is not seen at the SCK pin. Figure A-10 SPI Master Timing (CPHA = 0) ...
Page 150
... Freescale Semiconductor, Inc. SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (OUTPUT) 6 MOSI MSB IN (INPUT) NOTE: Not defined but normally MSB of character just received. Figure A-12 SPI Slave Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT MISO SEE ...
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... Freescale Semiconductor, Inc. Table A-9 EEPROM Characteristics V DD Characteristic Programming Time <1.0 MHz, RCO Enabled (Note 1) 1.0 to 2.0 MHz, RCO Disabled 2.0 MHz (or Anytime RCO Enabled) Erase Time (Note 1) Byte, Row and Bulk Write/Erase Endurance (Note 2) Data Retention (Note 2) NOTES: 1. The RC oscillator (RCO) must be enabled (by setting the CSEL bit in the OPTION register) for EEPROM pro- gramming and erasure when the E-clock frequency is below 1 ...
Page 152
... Freescale Semiconductor, Inc. ELECTRICAL CHARACTERISTICS A-18 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
Page 153
... Freescale Semiconductor, Inc. APPENDIX BMECHANICAL DATA AND ORDERING INFORMATION B.1 Pin Assignments The MC68HC11F1 is available in the 80-pin plastic low profile quad flat pack (LQFP) or the 68-pin plastic leaded chip carrier (PLCC). Refer to Table B-1 for ordering infor- mation. PC1/DATA1 10 PC2/DATA2 11 PC3/DATA3 ...
Page 154
... Freescale Semiconductor, Inc PB6/ADDR14 3 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PF7/ADDR7 10 PF6/ADDR6 11 PF5/ADDR5 12 PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 17 PE0/AN0 18 PE4/AN4 Figure B-2 MC68HC11F1 80-Pin Quad Flat Pack B.2 Package Dimensions For case outlines please visit our website at http://design-net.sps.mot.com. B-2 For More Information On This Product, MC68HC11F1 Go to: www ...
Page 155
... C 2 MHz 3 MHz – MHz 3 MHz 4 MHz – 105 C 2 MHz 3 MHz 4 MHz – 125 C 2 MHz 3 MHz Go to: www.freescale.com MC Order Number MC68HC11F1CPU2 MC68HC11F1CPU3 MC68HC11F1CPU4 MC68HC11F1VPU2 MC68HC11F1VPU3 MC68HC11F1VPU4 MC68HC11F1MPU2 MC68HC11F1MPU3 MC68HC11F1CFN2 MC68HC11F1CFN3 MC68HC11F1CFN4 MC68HC11F1VFN2 MC68HC11F1VFN3 MC68HC11F1VFN4 MC68HC11F1MFN2 MC68HC11F1MFN3 B-3 ...
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... Freescale Semiconductor, Inc. B-4 For More Information On This Product, Go to: www.freescale.com MC68HC11F1 TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. APPENDIX CDEVELOPMENT SUPPORT C.1 MC68HC11F1 Development Tools The following table and text provide a reference to development tools for the MC68HC11F1 microcontrollers. For more complete information refer to the appropri- ate manual for each system. Table C-1 MC68HC11F1 Development Tools Device MC68HC11F1 * For MC68HC11F1 support, the MMDS11 must be used with an MC68HC11F1 emulator module ...
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... Freescale Semiconductor, Inc. • Built-in real-time bus state analyzer: — 8 Kbyte x 64 real-time trace buffer — Four hardware triggers control real-time bus analysis, provide breakpoints — Nine triggering modes — Display of real-time trace data as raw data, disassembled instructions, raw data and disassembled instructions, or assembly-language source code — ...