ISPLSI2064V-80LT44 Lattice Semiconductor Corp., ISPLSI2064V-80LT44 Datasheet

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ISPLSI2064V-80LT44

Manufacturer Part Number
ISPLSI2064V-80LT44
Description
3.3V High Density Programmable Logic
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPLSI2064V-80LT44

Case
QFP
• HIGH DENSITY PROGRAMMABLE LOGIC
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
• HIGH-PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064v_10
Features
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 3.3V In-System Programmability (ISP™) Using
— Open-Drain Output Option for Flexible Bus Interface
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
f
t
Boundary Scan Test Access Port (TAP)
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
Market and Improved Product Quality
Machines, Address Decoders, etc.
5V ispLSI 2064
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 100MHz Maximum Operating Frequency
pd = 7.5ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Description
3.3V High Density Programmable Logic
A0
A2
A3
A1
A4
GLB
Output Routing Pool (ORP)
ispLSI
B7
A5
Global Routing Pool
Output Routing Pool (ORP)
Logic
Array
Input Bus
(GRP)
D Q
D Q
D Q
D Q
B6
Input Bus
A6
B5
A7
®
September 2000
B4
2064V
B0
B3
B2
B1
0139A/2064V

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ISPLSI2064V-80LT44 Summary of contents

Page 1

... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool ...

Page 3

Absolute Maximum Ratings Supply Voltage V cc ................................................... Input Voltage Applied ..................................... -0.5 to +5.6V Off-State Output Voltage Applied .................. -0.5 to +5.6V Storage Temperature ..................................... -65 to 150 C Case Temp. with Power Applied .................... -55 to 125 C ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...

Page 5

External Timing Parameters 4 TEST 2 PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f max (Ext.) – ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay io t din 21 Dedicated Input Delay GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

Page 7

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE 0 Derivations of su, h and co from the Product Term Clock Logic ...

Page 8

Power Consumption Power consumption in the ispLSI 2064V device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax I CC can ...

Page 9

Pin Description 84-PIN PLCC NAME PIN NUMBERS I I/O 3 26, 27, 28, I I/O 7 30, 31, 32, I I/O 11 34, 35, 36, I I/O 15 38, 39, 40, I/O ...

Page 10

Pin Description 44-PIN PLCC NAME PIN NUMBERS I I/O 3 15, 16, 17, I I/O 7 19, 20, 21, I I/O 11 25, 26, 27, I I/O 15 29, 30, 31, I/O ...

Page 11

Pin Configuration ispLSI 2064V 100-Pin TQFP Pinout Diagram RESET 11 VCC ...

Page 12

Pin Configuration ispLSI 2064V 84-Pin PLCC Pinout Diagram I I I/O 60 ...

Page 13

Pin Configuration ispLSI 2064V 44-Pin PLCC Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064V 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O ...

Page 14

Part Number Description ispLSI Device Family Device Number Speed f 100 = 100 MHz max MHz max MHz max ispLSI 2064V Ordering Information FAMILY fmax (MHz) tpd (ns) 100 7.5 100 7.5 ...

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