ISPLSI1032-60LT Lattice Semiconductor Corp., ISPLSI1032-60LT Datasheet

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ISPLSI1032-60LT

Manufacturer Part Number
ISPLSI1032-60LT
Description
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPLSI1032-60LT

Case
TQFP
Dc
06+

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPLSI1032-60LT
Manufacturer:
LAT
Quantity:
74
Part Number:
ISPLSI1032-60LT100
Manufacturer:
LATTICE
Quantity:
20 000
• HIGH-DENSITY PROGRAMMABLE LOGIC
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• COMBINES EASE OF USE AND THE FAST SYSTEM
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032_07
Features
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
— 100% Tested
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
SPEED OF PLDs WITH THE DENSITY AND FLEX-
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
f
f
t
Market, and Improved Product Quality
Machines, Address Decoders, etc.
Logic and Structured Designs
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 90 MHz Maximum Operating Frequency
max = 60 MHz for Industrial and Military/883 Devices
pd = 12 ns Propagation Delay
2
CMOS Technology
2
CMOS
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Functional Block Diagram
Description
A0
A1
A2
A3
A4
A5
A6
A7
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
Global Routing Pool (GRP)
Output Routing Pool
Output Routing Pool
ispLSI
Logic
Array
D Q
D Q
D Q
D Q
GLB
®
1032
March 1999
CLK
C6
C5
C4
C3
C2
C1
C0
C7

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ISPLSI1032-60LT Summary of contents

Page 1

... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 1032 Functional Block Diagram RESET Generic Logic Blocks (GLBs) I I/O 1 I I I I/O 9 ...

Page 3

Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...

Page 4

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) Test Condition R1 A ...

Page 5

External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...

Page 6

Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp 20 I/O Register Bypass t iolat 21 I/O Latch Delay t iosu 22 I/O Register Setup Time before Clock t ioh 23 I/O Register Hold Time after Clock t I/O ...

Page 7

Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs Output Buffer Delay t I/O Cell OE to Output Enabled oen 48 t odis 49 I/O Cell OE to Output Disabled Clocks t gy0 Clock Delay Global ...

Page 8

Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register D Q RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h and co ...

Page 9

Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1032 device depends on two primary factors: the speed at which the device is operating, and the number of Product ...

Page 10

Pin Description Name PLCC Pin Numbers I I/O 3 26, 27, I I/O 7 30, 31, I I/O 11 34, 35, I I/O 15 38, 39, I I/O 19 45, ...

Page 11

Pin Description Name TQFP Pin Numbers I I/O 3 17, 18, I I/O 7 21, 22, I I/O 11 29, 30, I I/O 15 33, 34, I I/O 19 40, ...

Page 12

Pin Description Name CPGA Pin Numbers I I/O 3 F1, H1, I I/O 7 K1, J2, I I/O 11 K3, L2, I I/O 15 L4, J5, I I/O 19 L7, ...

Page 13

Pin Configuration ispLSI 1032 84-Pin PLCC Pinout Diagram I I I/O 60 ...

Page 14

Pin Configuration ispLSI 1032 100-pin TQFP Pinout Diagram ...

Page 15

Pin Configuration ispLSI 1032/883 84-Pin CPGA Pinout Diagram I/O38 I/O41 I/O42 I/O36 I/O39 I/O40 I/O35 I/O37 I/O33 I/O34 Y1 IN4 I/O32 Vcc I/O31 GND *SCLK IN3 I/O30 I/O29 I/O28 I/O26 I/O27 I/O25 I/O23 I/O24 I/O22 ...

Page 16

Part Number Description ispLSI Device Family Device Number Speed MHz max MHz max MHz max Ordering Information f Family ispLSI f Family ispLSI f Family max (MHz) ispLSI ...

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