1.0 Pin Descriptions
1.1 Pin Assignments
Table 1-1. Hardware Signal Definitions (1 of 8)
Motorola Bus mode
Data Bus or Address
Data Strobe or
or Write Strobe
Fully Integrated T1/E1 Framer and Line Interface
Microprocessor Interface (MPU)
RST* low-to-high transition forces registers to their default, power-up
state and forces all PIO pins to the input state. RST* is not mandatory,
because internal power on reset circuit performs an identical function.
RST* can be applied asynchronously, but must remain asserted for a
minimum of 2 clock cycles (external MCLK or internal 32 MHz) for the
low-to-high transition to be sampled and detected (see also [RESET; addr
System applies MCLK in the range of 8–36 MHz for external clock
(CLKMD = 1) and synchronous bus modes (SYNCMD = 1). During internal
clock modes (CLKMD = 0), the Bt8370/8375/8376 uses an internally
generated 32 MHz clock to control processor timing, and MCLK input is
Selects Intel- or Motorola-style microprocessor interface. DS*, R/W*,
A[8:0], and AD[7:0] functions are affected.
0 = Motorola; AD[7:0] is data, A[8:0] is address, DS* is data strobe,
and R/W* indicates the read (high) or write (low) data direction.
1 = Intel; AD[7:0] is multiplexed address/data, A[7:0] ignored, A is
address line, DS* is read strobe (RD*), and R/W* is write strobe (WR*).
Selects whether read/write cycle timing is synchronous with MCLK.
Supports Intel- or Motorola-style buses:
0 = Asynchronous bus; read data enable and write data input latch are
asynchronously controlled by CS*, DS*, and R/W* signals. Latched write
data is still synchronized internally to 32 MHz clock for transfer to
1 = Synchronous bus; applicable only if the external clock is also
selected (CLKMD = 1). MCLK rising edge samples CS*, DS*, and R/W* to
determine valid read/write cycle timing. Allows 0 wait state processor
cycles for MCLK speeds up to 36 MHz, for M68000 type buses.
Selects whether MCLK is enabled (high) or ignored (low). When enabled,
MCLK frequency determines update rate of internal registers and sampling
rate of CS*, DS*, and R/W* signals.
AS* falling edge asynchronously latches A[8:0] (Motorola) or A (Intel)
to identify 1 register for subsequent read/write data transfer cycle.
Multiplexed address/data (Intel) or only data (Motorola). Refer to MOTO*
For all processor bus modes, AS* falling edge asynchronously latches
address from A[8:0] (Motorola) or from A and AD[7:0] (Intel). For sync
modes (SYNCMD = 1), each read/write data cycle requires both AS* and
CS* active-low on MCLK rising edge.
Active-low enables read/write decoder. Active-high ends current read or
write cycle and places data bus output in high impedance.
Active-low read data strobe (RD*) for MOTO* = 1, or read/write data
strobe (DS* ) for MOTO* = 0.
Active-low write data strobe (WR*) for MOTO* = 1, or read/write data
select (R/W*) for MOTO = 0.