BT8370KPF

Manufacturer Part NumberBT8370KPF
DescriptionFully integrated T1/E1 framer and line interface
ManufacturerConexant Systems, Inc.
BT8370KPF datasheet
 


Specifications of BT8370KPF

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Page 21/323:

Line Interface Unit (LIU)

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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
Table 1-1. Hardware Signal Definitions (2 of 8)
Pin Label
Signal Name
Microprocessor Interface (MPU) (Continued)
ONESEC
1-second Timer
INTR*
Interrupt Request
DTACK*
Data Transfer
Acknowledge
XOE
Transmit Output
Enable
RTIP, RRING
Receive Tip/Ring
VSET
Voltage Reference Set
XTIP, XRING
Transmit Tip/Ring
TCKI
Tx Clock Input
ACKI
All Ones Clock
N8370DSE
I/O
Definition
PIO
Controls or marks 1-second interval used for status reporting. When
input, the timer is aligned to ONESEC rising edge. When output, rising
edge indicates start of each 1-second interval. Typically, 1 device in a
multi-line system is configured to output ONESEC to synchronize other
Bt8370/8375/8376 status reports on a common 1-second interval.
O
Open drain active-low output signifies 1 or more pending interrupt
requests. INTR* goes to high-impedance state after processor has
serviced all pending interrupt requests.
O
Open drain active-low output signifies in-progress data transfer cycle.
DTACK* remains asserted (low) for as long as AS* and CS* are both
active-low. DTACK* is only implemented during synchronous Motorola
processor interface modes. Refer to the timing diagrams in
MPU Interface Timing
.

Line Interface Unit (LIU)

I
Active-high input enables XTIP and XRING output drivers; otherwise, both
outputs are placed in high-impedance state. XOE contains internal pullup
so systems that do not require three-stated outputs can leave XOE
unconnected. XOE needs to be disabled during Power-On Reset (POR) and
re-enabled after configuring the part. Refer to Power-On Reset procedure
in
Section 2.10.4, Device Reset
.
I
Differential AMI data inputs for direct connection to receive transformer.
I/O
Constant voltage output. Must be connected to an external 1% resistor
equal to 14 k to ground (GND[4] pin 62). The VSET resistor sets the
internal precision current reference of 100 A and also controls the
transmit pulse height.
O
Complementary AMI data outputs for direct connection to transmit
transformer. Optionally, both outputs are three-stated when XOE is
negated.
Digital Transmitter (XMTR)
I
Primary TX line rate clock applied on TCKI, or the system chooses from 1
of four different clocks to act as TX clock source (see [CMUX; addr 01A]).
The selected source is used to clock digital transmitter signals TPOSI,
TNEGI, TPOSO, TNEGO, TNRZO, MSYNCO, TDLI, and TDLCKO. If TSLIP is
bypassed, selected source also clocks TSB signals.
I
System optionally applies ACKI for AIS transmission, if the selected
primary transmit clock source fails. ACKI is either manually or
automatically switched to replace TCKI (see [AISCLK; addr 068]). Systems
without an AIS clock must tie ACKI to ground.
Conexant
1.0 Pin Descriptions
1.1 Pin Assignments
Section 5.5,
1-5