BT8370KPF

Manufacturer Part NumberBT8370KPF
DescriptionFully integrated T1/E1 framer and line interface
ManufacturerConexant Systems, Inc.
BT8370KPF datasheet
 


Specifications of BT8370KPF

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3.17 System Bus Registers
Output Sync on Falling Edge Clock—Selects TSBCKI rising or falling edge clock signal for
TSYN_NEG
TFSYNC or TMSYNC outputs. Opposite TSBCKI edge is used if TFSYNC or TMSYNC is
programmed as input.
When TFSYNC or TMSYNC is an input and configured for rising edge sampling,
TFSYNC or TMSYNC must be sampled low during the previous falling clock edge, then
sampled high at the rising clock edge. (Refer to
for RFSYNC/RMSYNC and TFSYNC/TMSYNC Input Signals
and Hold
Timing.)
Transmit System Bus Multiframe Aligns to Transmit Timebase—Allows multiframe
TSB_ALIGN
alignment located at TX timebase to pass across TSLIP and forces the corresponding
multiframe alignment onto the TSB timebase. Used primarily to pass CAS or MFAS alignment
located by the transmit online framer onto the TMSYNC output.
Force TSLIP to Center—Writing a 1 to TSB_CTR forces TSLIP read buffer pointer to its
TSB_CTR
initial delay condition, possibly forcing a change of transmit frame alignment if TSLIP is
configured in Elastic or Bypass modes. Writing a 0 has no effect. The processor must assert
TSB_CTR after configuration of the transmit slip buffer, after which, Bt8370/8375/8376
automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP
does not effect TSLIP status reported in ISR5[addr 006].
Transmit Slip Buffer Interface mode—Selects the configuration of the TSLIP buffer. The TSBI
TSBI[1:0]
determines the total buffer depth and initial delay conditions. While TSLIP is bypassed, TCKI
clocks the TSB input/output, and TSBCKI is ignored.
TSBI
Mode
00
Normal
01
Short
10
Elastic
11
Bypass
Bypass requires system bus equal to line rate.
NOTE(S):
To guarantee the pointer is initialized properly in the slip buffer during Elastic Mode,
the following procedure can be applied:
1.
2.
3.
3-118
Fully Integrated T1/E1 Framer and Line Interface
0 = TFSYNC or TMSYNC rising edge output (falling edge input)
1 = TFSYNC or TMSYNC falling edge output (rising edge input)
Figure 5-5, SBI Timing: Setup and Hold Time
0 = TSB multiframe does not follow XMTR
1 = TSB multiframe aligned by XMTR
0 = no effect
1 = force TSLIP to center
Total Depth
Initial Delay
2 Frame
0.5 to 1.5 Frames
2 Frame
32 Bits
64 Bits
32 Bits
0 Bits
0 Bits
Disable Slip Buffer
Center Slip Buffer
Set the Slip Buffer to Elastic mode
Conexant
Bt8370/8375/8376
and
Table 5-6, Input Data Setup
Conditions
Dependent on present depth, no
change of output frame.
Reverts to normal upon slip
Recenters automatically upon slip
TSBCKI ignored
TSBI[1:0] = 11, TSB_CTR = 0
TSBI[1:0] = 11, TSB_CTR = 1
TSBI[1:0] = 10, TSB_CTR = 0
N8370DSE