BT8370KPF Conexant Systems, Inc., BT8370KPF Datasheet - Page 240

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BT8370KPF

Manufacturer Part Number
BT8370KPF
Description
Fully integrated T1/E1 framer and line interface
Manufacturer
Conexant Systems, Inc.
Datasheet

Specifications of BT8370KPF

Case
QFP
3.17 System Bus Registers
Signaling State During Current Multiframe
New Input
Buffered Input
Signaling Bit
Signaling Bit
from Previous
Multiframe
(RSIGn[3:0])
0
0
1
0
1
1
0
1
1
1
0
1
0
0
1
0
Non-Debounced signaling always transfers buffered ABCD input to buffered ABCD output coincident with the
NOTE(S):
D-bit update.
Manual Signaling Update and SIGFRZ Output—Allows the processor to manually control
FRZ_OFF/FRZ_ON
updates of the receive signaling buffer [RSIGn; addr 1A0–1BF], the signaling stack [addr
0DA], and the SIGFRZ output pin. FRZ_ON and FRZ_OFF control the SIGFRZ pin’s output
state, but do not affect normal operations of the SIGFRZ interrupt [ISR7; addr 004]. The
receive ABCD input signaling is placed into the STACK and RSIG buffers according to the
modes shown below. Stack updates are individually enabled on a per-channel basis according
to SIG_STK [addr 180–19F].
FRZ_ON
FRZ_OFF
0
0
0
0
0
0
X
1
X
1
1
0
Enable Transparent Robbed-Bit Signaling—RMSYNC is forced to align with respect to RX
THRU
timebase and follow each change of receiver's multiframe alignment, plus any frame offset
caused by RSLIP buffer delay. In this manner, RMSYNC is able to retain its signaling
multiframe alignment with respect to RPCMO output data frames. THRU mode is required
when RSLIP is configured in Bypass mode. It is also useful for ADPCM transcoder systems
that utilize robbed-bit signaling during frames other than normal (modulo 6) signaling frames,
and therefore cannot utilize RPCMO signaling reinsertion in ADPCM coded channels. During
THRU mode, RMSYNC must be programmed as an output [PIO; addr 018]. RMSYNC can
follow a change of RX multiframe alignment without generating an alarm indication (e.g.,
receiver change of SF alignment without accompanying loss of basic frame alignment).
3-122
Fully Integrated T1/E1 Framer and Line Interface
Signaling State Updated at the End of Current Multiframe
Buffered Output
Buffered Input
Signaling Bit
Signaling Bit is
(RSIGn[7:4])
Updated from Input
Signaling
Bit (RSIGn[3:0])
0
0
0
1
0
1
0
0
1
1
1
0
1
0
1
1
SIGFRZ
SIG_STK
Interrupt
Pin
0
0
0
X
1
1
1
0
0
0
X
0
1
X
0
X
X
1
0 = no effect
1 = transparent robbed-bit signaling
Conexant
Bt8370/8375/8376
Buffered Output
Notes
Signaling Bit
(RSIGn[7:4])
0
0
1
Change Output
0
Debounce
1
1
0
Change Output
1
Debounce
STACK
RSIGn
No update
All ABCD
No update
No update
ABCD Changes
All ABCD
No Update
All ABCD
ABCD Changes
All ABCD
No update
No Update
N8370DSE

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