BT8370KPF

Manufacturer Part NumberBT8370KPF
DescriptionFully integrated T1/E1 framer and line interface
ManufacturerConexant Systems, Inc.
BT8370KPF datasheet
 


Specifications of BT8370KPF

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Data Recovery

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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
2.2.1 Data Recovery
The RLIU recovers data from the received analog signal by normalizing the
signal with the Variable Gain Amplifier (VGA) and the Automatic Gain Control
(AGC), removing distortion with the Adaptive Equalizer, and extracting the data
using the Data Slicer.
2.2.1.1 Automatic Gain
The AGC circuit adjusts the gain of the incoming differential signal to achieve a
Control
normalized level. The normalized level ensures that the input signal to the ADC is
75% to 100% of full scale. This is done by measuring the peak voltage of the
incoming signal with a peak detector, and inversely adjusting VGA gain based the
peak value. The AGC can be forced to a fixed gain for test purposes or limited to
a maximum value, which is the normal operating mode (see [FORCE_VGA;
addr 020]).
2.2.1.2 Variable Gain
The FORCE_VGA bit in the LIU Configuration register [LIU_CR; addr 020]
Amplifier
selects whether the AGC operates in Gain Limit mode or Fixed Gain mode. In
Gain Limit modes, the RLIU sensitivity is initially set to the maximum
(approximately 43 dB), and the gain is adjusted based the peak value recorded
during the AGC observation period. The AGC observation period can be set to 32,
128, 512, or 2048 symbol periods [RLIU_CR; addr 022]. A short observation
period allows quick responses to pulse height variations but possible overshoots.
A long observation period minimizes overshoots, but does not react quickly to
pulse height variations. The real-time status of the VGA gain setting can be read
in the Variable Gain Amplifier Status register [VGA; addr 029] and used to
approximate the receive analog signal level.
In Fixed Gain mode, the RLIU sensitivity is set to the value stored in the
Variable Gain Amplifier Maximum register [VGA_MAX; addr 024]. VGA_MAX
is a 6-bit register that allows up to 64 gain settings in 1.25 dB steps.
2.2.1.3 Adaptive
After the input amplitude has been normalized, the adaptive equalizer attempts to
Equalizer
remove the distortion introduced by the cable. The transfer function of the
equalizer is initially adjusted based on the peak value of the input signal because
this value provides some indication of the line length on the input. The Adaptive
Equalizer then automatically fine tunes to remove most of the signal distortion
due to intersymbol interference, noise, and other cable length effects.
In certain applications the device can be connected to a DSX monitor point
that has been resistively attenuated. Because this resistive attenuation adds no
phase-versus-frequency distortion, the VGA gain must be adjusted. This is done
by configuring the Receive Pad Resistor Compensation (ATTN[1,0]) in the LIU
Configuration register [LIU_CR; addr 020]. The resistive attenuation can be
configured to be either 0, –10, –20, or –30 dB.
2.2.1.4 Data Slicer
The Data Slicer extracts the data from the equalized signal by comparing the
differential inputs to threshold values. The threshold values are dynamically set,
based on a percentage of the peak level obtained by the peak detector. The
percentage is 50% of peak for both DS1 and CEPT. Dynamically adjusting the
threshold values ensures optimum signal-to-noise ratio. If the SQUELCH bit is
set in the LIU Configuration register [LIU_CR; addr 020] and the input signal
level is below threshold for the entire AGC observation period (EYEOPEN = 0),
Data Slicer output is forced to all 0s.
N8370DSE
2.2 Receive Line Interface Unit
Conexant
2.0 Circuit Description
2-7