Fully Integrated T1/E1 Framer and Line Interface
2.4.1 ZCS Decoder
The Receive Zero Code Suppression (RZCS) decoder decodes the dual rail data
(bipolar) into single rail data (unipolar). The Receive AMI bit (RAMI) in the
Receiver Configuration register [RCR0; addr 040] controls whether the received
signal is B8ZS/HDB3 decoded, depending on T1/E1N [addr 001] line rate
selection, or depending on whether the RZCS decoder is bypassed. If the line
code is unknown, the ZCSUB bit in Receive LIU Status [RSTAT; addr 021]
indicates that 1 or more B8ZS/HDB3 substitution patterns have been received on
the RTIP/RRING input. If the line code is B8ZS/HDB3 encoded, the RZCS bit in
RCR0 must be set to keep the LCV counter from counting BPVs that are part of
the B8ZS/HDB3 code.
2.4.2 In-Band Loopback Code Detection
The in-band loopback code detector circuitry detects receive data with in-band
codes of configurable value and length. These codes can be used to request
loopback of terminal equipment signals or other user-specified applications. The
two codes are referred to as loopback-activate and loopback-deactivate, although
the detectors need not be used only for loopback codes. Generally, any repeating
1–7 bit pattern can be selected. The loopback application is described in Section
9.3.1 of ANSI T1.403-1995. The loopback activate code is set in the Loopback
Activate Code Pattern [LBA; addr 043]. The loopback deactivate code is set in the
Loopback Deactivate Code Pattern [LBD; addr 044].
The sequence length for the loopback activate and deactivate codes can be
programmed for 4, 5, 6, or 7 bits by setting the code length bits of the Receive
Loopback Code Detector Configuration register [RLB; addr 042]. Shorter codes
can be programmed by repeating the expected pattern (e.g., 3+3 bit code
programmed as 6-bit code).
When a loopback code is detected, the LOOPUP or LOOPDN status bit is set
in Alarm 2 register [ALM2; addr 048], and the corresponding LOOPUP or
LOOPDN bit in Alarm 2 Interrupt Status register (ISR6; addr 005] is set. The
loopback detection interrupt can be enabled using the Alarm 2 Interrupt Enable
register [IER6; addr 00D]. When enabled, a loop-up or loop-down code detection
causes the Alarm 2 Interrupt bit [ALARM2] to be set in the Interrupt Request
register [IRR; addr 003] and generates an interrupt. Since loopbacks are not
automatically initiated, the processor must intercept and interpret the interrupt
status condition to determine when it must enable or disable the loopback control
mechanism (e.g., LLOOP; addr 014).
The in-band loopback code detector circuitry is only applicable to T1 mode.
T1 In-Band Loopback Codes
2.0 Circuit Description