2.0 Circuit Description
2.4.8 External Receive Data Link
The External Data Link (DL3) provides signal access to any bit(s) in any time slot
of all frames, odd frames, or even frames, including T1 framing bits. Pin access to
the DL3 receiver is provided through RDLCKO and RDLO. These two pins serve
as the DL3 clock output (RDLCKO) and data output (RDLO). The data link
mode of the pins is selected using the RDL_IO bit in the Programmable
Input/Output register [PIO; addr 018].
Control of DL3 is provided in two registers: External Data Link Channel
[DL3_TS; add 015] and External Data Link Bit [DL3_BIT; addr 016]. RDL3 is
set up by selecting the bit(s) (DL3_BIT) and time slot [TS[4:0]; addr 015] to be
monitored, and then enabling the data link [DL3EN; addr 015], which starts the
RDLCKO and TDLCKO gapped clock outputs that mark the selected bits, as
Figure 2-12. Receive External Data Link Waveforms
F 1 2
24 F 1
This waveform represents time slot 1 extraction. Any combination of bits can be selected.
2.4.9 Sa-Byte Receive Buffers
The Sa-Byte buffers give read access to the odd frame Sa bits in E1 mode. Five
receive Sa-Byte buffers [RSA4 to RSA8; addr 05B to 05F] are available. As a
group, the buffers are updated every multiframe from Sa-bits received in TS0.
This gives the processor up to 2 ms after the receive multiframe interrupt [RMF;
addr 008] occurs to read any Sa-Byte buffer before the buffer content changes.
2.4.10 Receive Data Link
The RCVR contains two independent data link controllers (DL1 and DL2) and a
Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to
send and receive HDLC formatted messages in the Message-Oriented Protocol
(MOP) mode. Alternatively, unformatted serial data can be sent and received over
any combination of bits within a selected time slot or F-bit channel. The BOP
transceiver can preemptively receive and transmit BOP messages, such as ESF
Fully Integrated T1/E1 Framer and Line Interface
24 F 1 2