Fully Integrated T1/E1 Framer and Line Interface
Using the receive FIFO, an entire block of data can be received with very little
microprocessor interrupt overhead. Block transfers from the FIFO can be
controlled by the Near Full Threshold in the FIFO Fill Control register
[RDL1_FFC; addr 0A7]. The Near Full Threshold is a user-programmable value
between 0 and 63. This value represents the maximum number of bytes that can
be placed into the receive FIFO without the near full being declared. Once the
threshold is set, the Near Full Status (RNEAR1) in RDL #1 Status [RDL1_STAT;
addr 0A9] is asserted when the Near Full Threshold is reached. An interrupt,
RNEAR, in Data Link 1 Interrupt Status [ISR2; addr 009], is also available to
mark this event.
The Bt8370/8375/8376 uses a hierarchical interrupt structure, with 1 top-level
interrupt cause register directing software to the lower levels (see Interrupt
Request register; addr 003). Of all the interrupt sources, the two most significant
bandwidth requirements are signaling and data link interrupts. Each data link
controller has a top-level interrupt status register that reports data link operations
(see Data Link 1 and 2 Interrupt Status registers [ISR2, ISR1; addr 009 and 00A).
The processor uses a two-step interrupt scheme for the data link:
22.214.171.124 RBOP Receiver
The Receive Bit-Oriented Protocol (RBOP) receiver receives BOP messages,
including the ESF Yellow Alarm, which consists of repeated 16-bit patterns with
an embedded 6-bit codeword as shown in this example:
The BOP message channel is configured to operate over the same channel
selected by Data Link #1 [DL1_TS; addr 0A4]. It must be configured to operate
over the FDL channel so RBOP can detect priority, command, and response
codeword messages according to ANSI T1.403, Section 9.4.1.
RBOP is enabled using the RBOP_START bit in Bit Oriented Protocol
Transceiver register [BOP; address 0A0]. BOP codewords are received in the
Receive BOP Codeword register [RBOP; addr 0A2], which contains the 6-bit
codeword, a valid flag (RBOP_VALID), and a lost flag (RBOP_LOST). The valid
flag is set each time a new codeword is put in RBOP, and is cleared on reading the
codeword. The lost flag indicates a new codeword overwrote a valid codeword
before the processor read it.
The BOP receiver can be configured to update RBOP using a message length
filter and integration filter. The receive BOP message length filter [RBOP_LEN;
addr 0A40] sets the number of successive identical messages required before
RBOP is updated. RBOP_LEN can be set to 1, 10, and 25 messages. When
enabled, the RBOP integration filter [RBOP_INTEG; add 0A0] requires receipt
of two identical consecutive 16-bit patterns, without gaps or errors between
patterns, to validate the first codeword. RBOP integration is needed to meet the
codeword detection criteria while receiving 1 1/1000 bit error ratio.
The real-time status of the codeword reception can be monitored using the
RBOP_ACTIVE bit in the BOP Status register [BOP_STAT; addr 0A3]. Each
time a message is put in RBOP register, an interrupt is generated, and the RBOP
bit is set in the Data Link 2 Interrupt Status register [ISR1; addr 00A].
It reads the Interrupt Request register.
It uses that register value to read the corresponding Data Link Interrupt
0xxxxxx0 11111111 (received right to left)
 RBOP = 6-bit codeword
2.0 Circuit Description