2.0 Circuit Description
2.5 Receive System Bus
2.5.2 Slip Buffer
The 64-byte Receive PCM Slip Buffer [RSLIP; addr 1C0 to 1FF] resynchronizes
the Receiver Clock (RXCLK) and data (RNRZ) to the Receive System Bus Clock
(RSBCK) and data (RPCMO). RSLIP acts like an elastic store by clocking RNRZ
data in with RXCLK and clocking PCM data out on RPCMO with RSBCK.
If the system bus rate is greater than the line rate (i.e., T1 line rate and E1
system bus rate), there is a mismatched number of time slots. The mapping of line
rate time slots to system bus time slots is done by time slot assignments with the
ASSIGN bit in the System Bus Per-Channel Control register [SBC0 to SBC31;
addr 0E0 to 0FF]. ASSIGN selects which system bus time slots are used to
transport line rate time slots. Time slot mapping is done by mapping the first line
rate time slot to the first assigned system bus time slot. For example, T1 to E1
mapping might make every fourth time slot unassigned (i.e., 3, 7, 11, 15, 19, 23,
27, 31); see
the idle time slots and optimizes the slip buffer use.
Figure 2-19. T1 Line to E1 System Bus Time Slot Mapping
1. u = unassigned time slots
RSLIP has four modes of operation: Two-Frame Normal, 64-bit Elastic,
Two-Frame Short, and Bypass. RSLIP mode is set in the Receive System Bus
Configuration register [RSB_CR; addr 0D1]. RSLIP is organized as a 2-frame
buffer. This allows MPU access to frame data, regardless of the RSLIP mode
selected. Each byte offset into the frame buffer is a different time slot: offset 0 in
RSLIP is always time slot 0 (TS0), offset 1 is always TS1, and so on. The slip
buffer has processor read/write access.
Fully Integrated T1/E1 Framer and Line Interface
2-19. This distribution of unassigned time slots averages out
All line rate time slots must be assigned to a system bus time slot.
= T1 frame bit for frame A
30 31 0