2.0 Circuit Description
2.5 Receive System Bus
2.5.4 Signaling Stack
The Receive Signaling Stack (RSTACK) allows the processor to quickly extract
signaling changes without polling every channel. RSTACK is activated on a
per-channel basis by setting the Received Signaling Stack (SIG_STK) control bit
in the Receive Per-Channel Control register [RPC0 to RPC31; addr 180 to 19F].
The signaling stack stores the channel and the A, B, C, and D signaling bits that
changed in the last multiframe. The stack has the capacity to store signaling
changes for all 24 (T1) or 30 (E1) PCM channels.
At the end of any multiframe where 1 or more ABCD signaling values have
changed, an interrupt occurs with RSIG set in the Timer Interrupt Status register
[ISR3; addr 008]. The processor then reads the Receive Signaling Stack [STACK;
addr 0DA] twice to retrieve the channel number (WORD = 0) and the new ABCD
value (WORD = 1), and continues to read from STACK until the MORE bit in
STACK is cleared, indicating the RSIG stack is empty.
Optionally, the processor can select RSIG interrupt (SET_RSIG; addr 0D7) to
occur at each multiframe boundary in T1 modes, regardless of signaling change.
This mode provides an interrupt aligned to the multiframe to read the RSIG buffer
rather than RSTACK.
2.5.5 Embedded Framing
Embedded Framing mode bit (EMBED; addr 0D0) instructs the RSB to embed
framing bits on RPCMO while in T1 mode.
The G.802 Embedded mode supports ITU-T Recommendation G.802, which
describes how 24 T1 time slots and 1 framing bit (193 bits) are mapped to 32 E1
time slots (256 bits). This mapping is done by leaving TS0 and TS16 unassigned,
by storing the 24 T1 time slots in TS1 to TS15 and TS17 to TS25, and by storing
the frame bit in bit 1 of TS26 (see
Figure 2-20. G.802 Embedded Framing
1. X = unused bits
2. u = unassigned time slot (see ASSIGN bit [addr 0E0 to 0FF])
= T1 frame bit for frame B
Fully Integrated T1/E1 Framer and Line Interface
2-20). TS26 through TS31 are also
15 16 17
16 17 18