2.0 Circuit Description
2.7 Transmit System Bus
The TSB timebase synchronizes TPCMI, TFSYNC, TMSYNC, and TINDO with
the Transmit System Bus Clock (TSBCK). The TSBCK can be slaved to five
different clock sources: Transmit Clock Input (TCKI), Transmit System Bus
Clock Input (TSBCKI), Receive System Bus Clock Input (RSBCKI), Clock Rate
Adapter Input (CLADI), or Clock Rate Adapter Output (CLADO).
The TSB clock selection is made through the Clock Input Mux register
[CMUX; addr 01A]. TCKI is automatically selected when the transmit slip buffer
is bypassed. The system bus clock can also be configured to run at twice the data
rate by setting the X2CLK bit in the System Bus Interface Configuration register
[SBI_CR; addr 0D0] when TSLIP is not in Bypass mode.
TFSYNC and TMSYNC can be individually configured as inputs or outputs
[PIO; addr 018]. TFSYNC and TMSYNC should be configured as inputs when
the TSB timebase is slaved to the system bus, when the transmit framer is
disabled [TABORT; addr 071], or when TSB carries embedded T1 framing.
TFSYNC and TMSYNC should be configured as outputs when the TSB timebase
is master of the system bus, or when the transmit framer is enabled. TFSYNC and
TMSYNC can also be configured as rising or falling edge outputs [TSB_CR; addr
0D4]. In addition to having TFSYNC and TMSYNC active on the frame
boundary, a programmable offset is available to select the time slot and bit offset
in the frame. See Transmit System Bus Sync time slot Offset [TSYNC_TS; addr
0D6] and Transmit System Bus Sync Bit Offset [TSYNC_BIT; addr 0D5].
2.7.2 Slip Buffer
The 64-byte Transmit PCM Slip Buffer [TSLIP; addr 140 to 17F] resynchronizes
the Transmit System Bus Clock (TSBCK) and data (TPCMI) to the Transmit
Clock (TXCLK) and data (TNRZ). TSLIP acts like an elastic store by clocking
PCM data in on TPCMI with TSBCK, and by clocking TNRZ data out with
TXCLK. TPCMI can be configured to sample on the rising or falling edge of
TSBCKI. See the Transmit System Bus Configuration register [TSB_CR; addr
TSLIP has four modes of operation: Two-Frame Normal, 64-bit Elastic,
Two-Frame Short, and Bypass. TSLIP mode is set in the Transmit System Bus
Configuration register [TSB_CR; addr 0D4]. It is organized as a two-frame
buffer, with high-frame and low-frame buffers. This allows MPU access to frame
data, regardless of the TSLIP mode selected. Each byte offset into the frame
buffer is a different time slot: offset 0 in TSLIP is always time slot 0 (TS0),
offset 1 is always TS1, and so on. The slip buffer has processor read/write access.
Fully Integrated T1/E1 Framer and Line Interface
The CLADO signal is not available in the Bt8376 device.