MPC949 Freescale Semiconductor, Inc, MPC949 Datasheet

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MPC949

Manufacturer Part Number
MPC949
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MPC949
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MPC949FAR2
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage 1:15 PECL to
CMOS Clock Driver
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The device features a low voltage PECL input, in
addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into
larger clock trees which utilize low skew PECL devices (see the
MC100LVE111 data sheet) in the lower branches of the tree. The fifteen
outputs were designed and optimized to drive 50Ω series or parallel
terminated transmission lines. With output to output skews of 300ps the
MPC949 is an ideal clock distribution chip for synchronous systems
which need a tight level of skew from a large number of outputs. For a
similar product with a smaller fanout and package consult the MPC946
data sheet.
the LOW logic states, the output buffers of the MPC949 are ideal for
driving series terminated transmission lines. More specifically each of the
15 MPC949 outputs can drive two series terminated transmission lines.
With this capability, the MPC949 has an effective fanout of 1:30 in
applications using point–to–point distribution schemes.
generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability
to allow the user to select the ratio of 1X outputs to 1/2X outputs.
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.
Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.
of the device. The 52–lead TQFP has a 10x10mm body size with a 0.65mm pin spacing.
Pentium is a trademark of Intel Corporation.
10/96
Motorola, Inc. 1996
Clock Distribution for Pentium
Low Voltage PECL Clock Input
2 Selectable LVCMOS/LVTTL Clock Inputs
350ps Maximum Output to Output Skew
Drives up to 30 Independent Clock Lines
Maximum Output Frequency of 150MHz
High Impedance Output Enable
52–Lead TQFP Packaging
3.3V V CC Supply
The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15
With an output impedance of approximately 7Ω, in both the HIGH and
The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
The MPC949 is fully 3.3V compatible. The 52 lead TQFP package was chosen to optimize performance, board space and cost
Systems with PCI
1
REV 1
1:15 PECL TO CMOS
52–LEAD TQFP PACKAGE
CLOCK DRIVER
LOW VOLTAGE
MPC949
CASE 848D–03
FA SUFFIX

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MPC949 Summary of contents

Page 1

... The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability to allow the user to select the ratio of 1X outputs to 1/2X outputs ...

Page 2

... Pullup) PCLK (Int Pulldown) PCLK (Int Pullup) Dseln (Int Pulldown) MR/OE (Int Pulldown) PCLK_Sel (Int Pulldown VCCd 24 Qd4 23 GNDd 22 Qd3 21 VCCd MPC949 20 Qd2 19 GNDd 18 Qd1 17 VCCd 16 Qd0 15 GNDd Function Select pin to choose TCKL0 or TCLK1 LVCMOS/LVTTL clock inputs True PECL clock input ...

Page 3

... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the V CMR range and the input swing lies within the V PP specification. 2. The MPC949 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). ...

Page 4

... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC949 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 5

... –M– 0.10 (0.004) T VIEW θ1 0.25 (0.010) θ GAGE PLANE MPC949 –X– X= VIEW Y BASE METAL F PLATING Ç Ç Ç Ç É É É É É É É É Ç Ç Ç Ç D 0.13 (0.005) T L– SECTION AB–AB ROTATED 90 _ CLOCKWISE NOTES: 1 ...

Page 6

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 MPC949/D TIMING SOLUTIONS BR1333 — Rev 6 ...

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