ISPLSI5512VA-110LQ208 Lattice Semiconductor Corp., ISPLSI5512VA-110LQ208 Datasheet

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ISPLSI5512VA-110LQ208

Manufacturer Part Number
ISPLSI5512VA-110LQ208
Description
110 MHz in-system prommable 3.3V superWIDE high density PLD
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPLSI5512VA-110LQ208

Case
QFP
• SuperWIDE HIGH-DENSITY IN-SYSTEM
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
• ARCHITECTURE FEATURES
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
5512va_08
Features
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 24000 PLD Gates / 512 Macrocells
— Up to 288 I/O Pins
— 512 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
— SuperWIDE Input Gating (68 Inputs) for Fast
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
— Enhanced
— TTL/3.3V/2.5V Compatible Input Thresholds and
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Debugging
3.3V IN-SYSTEM PROGRAMMABLE
— Enhanced Pin-Locking Architecture with Single-
— Wrap Around Product Term Sharing Array Supports
— Macrocells Support Concurrent Combinatorial and
— Macrocell Registers Feature Multiple Control
— Four Dedicated Clock Input Pins Plus Macrocell
— Slew and Skew Programmable I/O (SASPI/O)
— Six Global Output Enable Terms, Two Global OE
Market, and Improved Product Quality
Optimum Performance
Counters, State Machines, Address Decoders, etc.
f
t
t
Output Levels
Level Global Routing Pool and SuperWIDE GLBs
up to 35 Product Terms Per Macrocell
Registered Functions
Options Including Set, Reset and Clock Enable
Product Term Clocks
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
Pins and One Product Term OE per Macrocell
max = 110 MHz Maximum Operating Frequency
pd = 8.5 ns Propagation Delay
su3 (CLK2/3) = 3.5ns
t
su2 = 7 ns,
2
CMOS
t
su3 (CLK0/1) = 4.5ns,
®
TECHNOLOGY
1
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
Functional Block Diagram
ispLSI 5000V Description
3.3V SuperWIDE™ High Density PLD
Logic Block
Logic Block
Generic
Input Bus
Generic
Input Bus
ispLSI
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
Global Routing Pool
In-System Programmable
(GRP)
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
®
5512VA
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
January 2002
Boundary
Interface
Scan

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ISPLSI5512VA-110LQ208 Summary of contents

Page 1

... Six Global Output Enable Terms, Two Global OE Pins and One Product Term OE per Macrocell Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option) Input Bus Generic Logic Block VCCIO 1 I TOE I/O 1 I/O 2 I/O 3 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 ...

Page 3

Description (Continued) five extra product terms are used for shared GLB con- trols, set, reset, clock, clock enable and output enable. The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or ...

Page 4

Figure 2. ispLSI 5512VA Block Diagram (288 I/O Version I 160 Global 5 160 Routing PT PT Pool 5 160 (GRP I/O CLK2 160 ...

Page 5

Figure 3. ispLSI 5000V Generic Logic Block (GLB) From Global Routing Pool ...

Page 6

Figure 4. ispLSI 5000V Macrocell PTOE GOE0 GOE1 TOE Shared PT Clock 0 Shared PT Clock 1 PT Clock CLK0 CLK1 CLK2 CLK3 PT Reset SET/RESET Shared PT (P)reset 0 PT Preset Shared PT (P)reset 1 Programmable Speed/Power Option Specifications ...

Page 7

Global Clock Distribution The ispLSI 5000V Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest ...

Page 8

Figure 6. Boundary Scan Register Circuit for I/O Pins SCANIN BSCAN (from previous Registers cell Shift DR Clock DR Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN ...

Page 9

Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI T btch TCK TDO Data to be captured Data to be driven out SYMBOL t btcp TCK [BSCAN test] clock pulse width t btch TCK [BSCAN test] pulse width high ...

Page 10

Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...

Page 11

Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (See Figure 8) 3.3V TEST CONDITION R1 ...

Page 12

DC Electrical Characteristics for 2.5V Range SYMBOL PARAMETER V I/O Reference Voltage CCIO V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. I/O voltage configuration must be set ...

Page 13

External Switching Characteristics ...

Page 14

Internal Timing Parameters 2 PARAM # I/O Buffer t idcom 22 Input Pad and Buffer, Combinatorial Input t idreg 23 Input Pad and Buffer, Registered Input t odcom 24 Output Pad and Buffer, Combinatorial Output t odreg 25 Output Pad ...

Page 15

Internal Timing Parameters 2 PARAM # GRP t grpi 57 GRP Delay from I/O Pad t grpm 58 GRP Delay from Macrocell Global Control Delays t gclk01 59 Global Clock Delay t gclk23 60 Global Clock 2 ...

Page 16

Power Consumption Power consumption in the ispLSI 5512VA device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. ...

Page 17

Signal Descriptions Signal Name TMS Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the ...

Page 18

PQFP Signal Locations Signal GOE0, GOE1 78, 79 TOE / I/O0 32 GSET/GRST 138 TCK 29 TDI 30 TDO 136 TMS 28 CLK0, CLK1 184,185 CLK2 / I/O89 162 CLK3 / I/O98 173 VCCIO 137 GND 3, 12, 19, ...

Page 19

BGA Signal Locations Signal GOE0, GOE1 AF14, AD13 TOE / I/O0 T1 GSET/GRST L25 TCK T2 TDI R3 TDO N24 TMS R1 CLK0, CLK1 A13, C14 CLK2 / I/O179 A23 CLK3 / I/O197 B17 VCCIO M26 GND A1, A2, ...

Page 20

BGA I/O Locations (Sorted by I/O) I/O # I/O # Ball Ball AC9 AF8 AD8 AE9 AF9 AE10 ...

Page 21

BGA I/O Locations (Sorted by Ball) I/O # I/O # Ball Ball 246 A03 243 C05 242 A04 239 C06 238 A05 236 C07 235 A06 232 C08 231 A07 225 C10 228 A08 221 C11 226 A09 217 ...

Page 22

Signal Locations (272-Ball BGA) Signal GOE0, GOE1 V11, U11 TOE / I GSET/GRST J18 TCK L4 TDI M1 TDO J20 TMS L3 CLK0, CLK1 C10, D10 CLK2 / I/O 119 A18 CLK3 / I/O 131 B13 VCCIO J19 ...

Page 23

BGA I/O Locations (Sorted by I/O) I/O # I/O # Ball Ball ...

Page 24

BGA I/O Locations (Sorted by Ball) I/O # I/O # Ball Ball 121 B16 164 A2 116 B17 160 A3 169 C1 158 A4 166 C2 154 A5 162 C4 151 A6 156 C6 149 A7 152 C7 146 ...

Page 25

Signal Configuration ispLSI 5512VA 272-ball BGA I/O I/O I/O I/O CLK2 114 115 122 126 I/O 119 I/O I/O I 116 121 125 I/O ...

Page 26

Signal Configuration ispLSI 5512VA 388-ball BGA I/O I/O I/O 179/ I/O I/O I/O A GND 174 176 CLK2 183 187 189 I/O I/O I/O I/O I/O B GND GND 175 177 180 ...

Page 27

Pin Configuration ispLSI 5512VA 208-pin PQFP (with Heat Spreader) I/O 124 1 2 I/O 125 GND 3 I/O 126 4 I/O 127 5 6 I/O 128 VCC 7 I/O 129 8 I/O 130 9 I/O 131 10 I/O 132 11 ...

Page 28

Part Number Description ispLSI 5512VA Device Family Device Number Speed f 110 = 110 MHz max f 100 = 100 MHz max MHz max Ordering Information ...

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