MT352CG Zarlink Semiconductor, MT352CG Datasheet

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MT352CG

Manufacturer Part Number
MT352CG
Description
Manufacturer
Zarlink Semiconductor
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
MT352CG
Manufacturer:
ZARLINK
Quantity:
20 000
Features
Applications
Nordig II and ETSI 300 744 compliant
Superior Single Frequency Network performance
Unique active Impulse-Noise filtering
Single SAW operation
Automatic co-channel and adjacent-channel
interference suppression
Clock generation from single low-cost 20.48 MHz
crystal or external 4 or 27 MHz clock
IF sampling at 4.57, 36.17 or 43.5 MHz from a
single crystal frequency
Channel bandwidth of 6, 7 & 8 MHz
Blind acquisition capability (including 2K/8K
mode detect)
Automatic spectral inversion detection
Fast auto-scan and acquisition technology
Very low software overhead
Dual AGC control option
Access to channel SNR, pre- and post-Viterbi bit
error rates
Compact 64 pin LQFP
Less than 0.22W power consumption
Standby and sleep options
Set-top boxes
Integrated digital televisions
Personal video recorders
Terrestrial PC reception
Mobile and portable applications
RF in
Secondary
2-wire bus
ADC
AGC
Tuner control
conversion &
Suppression
Interpolator
Baseband
Impulse
IF to
Recovery
Carrier &
Figure 1 - Block Diagram
Symbol,
Timing
FFT
DS5792
Zarlink evaluation kits include application board, TNIM
and supporting software based on industry standard
operating systems. Device drivers are also available
enabling rapid product development and reduction in
time to market.
Description
MT352
Orthogonal Frequency Division Multiplex (COFDM)
television demodulator that is both Nordig II and DVB
(as defined in ETS 300 744 specification) compliant. It
can be used in
MHz channels and is capable of addressing all modes
of transmission.
The device includes a high performance 10-bit A/D
converter capable of accepting direct IF at 36.17 or
43.75 MHz.
frequencies in 6,7 or 8 MHz OFDM channels can be
generated from a single
Alternatively, there is provision to replace this crystal
with a 4 or 27 MHz external clock input.
Processor
Channel
Pilot &
MT352/GC/GP1N
is
a
Sampling rates required for both these
Control
engine
superior
either 2K or 8K modes with 6, 7 or 8
De-interleaver
Ordering Information
Symbol & Bit
& Demapper
0
o
COFDM Demodulator
C to +70
Issue 2
third
64 PIN LQFP
2-wire bus
o
Primary
20.48 MHz crystal.
C
generation
FEC
Data Sheet
November 2002
MPEG
MT352
TS
Coded
1

Related parts for MT352CG

MT352CG Summary of contents

Page 1

Features • Nordig II and ETSI 300 744 compliant • Superior Single Frequency Network performance • Unique active Impulse-Noise filtering • Single SAW operation • Automatic co-channel and adjacent-channel interference suppression • Clock generation from single low-cost 20.48 MHz crystal ...

Page 2

... Blind acquisition mode enables automatic detection of all OFDM signal parameters, including mode, guard and spectral inversion. The frequency capture range is sufficient to compensate for the combined offset introduced by the tuner and broadcaster. The device is packaged in a 64-pin LQFP and consumes less than 220 mW of power. 2 Figure 2 - Package Outline Zarlink Semiconductor Inc. Data Sheet ...

Page 3

... MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.3.1 MOCLKINV = 3.3.3.2 MOCLKINV = 4.0 Pin/package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Recommended operating conditions 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 Crystal specification and external clocking 6.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table of Contents Zarlink Semiconductor Inc. MT352 iii ...

Page 4

... MT352 iv Zarlink Semiconductor Inc. Data Sheet ...

Page 5

... Figure 6 - Primary 2-wire Bus Timing Figure 7 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - MPEG Output Data Waveforms Figure 9 - MPEG Timing - MOCLKINV = Figure 10 - MPEG Timing - MOCLKINV = Figure 11 - Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 List of Figures Zarlink Semiconductor Inc. MT352 v ...

Page 6

... MT352 vi Zarlink Semiconductor Inc. Data Sheet ...

Page 7

... Data Sheet Table 1 - Programmable address details for 2-wire bus in TNIM evaluation application . . . . . . . . . . . . . . . . . . . . 14 Table 2 - MOCLKINV = Table 3 - MDOSWAP = Table 4 - MDOSWAP = Table 5 - Pin descriptions List of Tables Zarlink Semiconductor Inc. MT352 vii ...

Page 8

... MT352 viii Zarlink Semiconductor Inc. Data Sheet ...

Page 9

... The controller facilitates the automated search of all parameters or any sub-set of parameters of the received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This Figure 3 - OFDM demodulator diagram Figure 4 - FEC Block Diagram Zarlink Semiconductor Inc. MT352 9 ...

Page 10

... A correction for spectral inversion is implemented during this conversion process. Note also that the MT352 has control mechanisms to search automatically for an unknown spectral inversion status. 10 Zarlink Semiconductor Inc. Data Sheet ...

Page 11

... This module also generates dynamic channel state information (CSI) for every carrier in every symbol. 1.11 Impulse Filtering MT352 contains several mechanisms to reduce the impact of impulse noise on system performance. Zarlink Semiconductor Inc. MT352 11 ...

Page 12

... Reed-Solomon decoder in MT352 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can be used to compute the post-Viterbi BER 3). Soft decisions for both Zarlink Semiconductor Inc. Data Sheet ...

Page 13

... Interfaces The MT352 interfaces to other parts of a terrestrial receiver system can be partitioned into three groups: the host controller, the tuner and the MPEG decoder. One other pin, the Status output, is multi-functional and can directly Figure 5 - Primary interfaces Zarlink Semiconductor Inc. MT352 13 ...

Page 14

... The MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control mode is selected by a single register control bit. The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2. 14 ADDR[5] ADDR[4] ADDR[3] SADD[4] SADD[3] SADD[2] VSS VDD VDD Zarlink Semiconductor Inc. Data Sheet ADDR[2] ADDR[1] SADD[1] SADD[0] VDD VDD ...

Page 15

... MT352 output W A RADD A DATA (n) (reg DATA A DATA (reg 0) (reg 1) RADD A S DEVICE R (n) ADDRESS Figure 6 - Primary 2-wire Bus Timing Zarlink Semiconductor Inc. W Write (=0) R Read (= 1) NA NOT Acknowledge RADD Register Address A DATA A P (reg n+1) A DATA NA P (reg 2) A DATA A DATA ...

Page 16

... CLK t BUFF t HD;STA t LOW t HIGH t SU;STA t HD;DAT t SU;DAT SU;STO Figure 7 - DVB Transport Packet Header Byte Zarlink Semiconductor Inc. Data Sheet Value Symbol Min Max 0 450 200 200 1300 600 200 100 100 note 1 20 200 Timing of 2-Wire Bus Unit kHz ns ns ...

Page 17

... MPEG Output Timing Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 70 Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = 0 MOCLK frequency = 61.44 MHz. Figure 8 - MPEG Output Data Waveforms o C, Output load = 10pF Output load = 10pF. Zarlink Semiconductor Inc. MT352 17 ...

Page 18

... Setup Time t SU Hold Time Maximum delay conditions Table 2 - MOCLKINV = 1 Figure 9 - MPEG Timing - MOCLKINV = 1 Maximum delay conditions 1.5 ns Table 3 - MDOSWAP = 0 Maximum delay conditions Table 4 - MDOSWAP = 1 Zarlink Semiconductor Inc. Minimum delay conditions 0 Minimum delay conditions 0 0.5 ns Minimum delay conditions 0 1.2 ns Data Sheet ...

Page 19

... Data Sheet Figure 10 - MPEG Timing - MOCLKINV = 0 Zarlink Semiconductor Inc. MT352 19 ...

Page 20

... MOSTRT MPEG packet start MOVAL MPEG data valid MDO(0:7) MPEG data bus MOCLK MPEG clock out BKERR Block error MICLK MPEG clock in STATUS Status output IRQ Interrupt output Zarlink Semiconductor Inc. Data Sheet I/O Type 3· 3·3 1 CMOS Tristate O 3· 3· ...

Page 21

... PLL supply PLLGND CVDD Core logic power VDD I/O ring power GND Core and I/O ground AVDD ADC analog supply AGND DVDD ADC digital supply DGND Table 5 - Pin descriptions. Zarlink Semiconductor Inc. MT352 I/O Type V I CMOS 5 I/O Open drain CMOS I 3· ...

Page 22

... VDD 3·0 core CVDD 1·62 1 periphery IDD P core IDD C XTI 16·00 fCLK 0 Symbol VDD CVDD TSTG TOP TJ Zarlink Semiconductor Inc. Data Sheet Typ. Max. 3·3 3·6 1·8 1·98 1 120 20·48 25·00 450 70 Min. Max. -0.3 +3.6 V -0.3 +2.0 V -0.3 5.5 V -0.3 VDD + 0 ...

Page 23

... GPP(3:0), DATA1, AGC1, AGC2 IRQ MICLK, SADD(4:0), SLEEP, OSCMODE Vin GPP(3:0), CLK1, DATA1, RESET Vin +5.5V All inputs SLEEP, SMTEST, MICLK, CLK1, OSCMODE SADD(4:0), DATA1, GPP(3:0) Zarlink Semiconductor Inc. MT352 Symbol Min Typ. Max VDD 3.0 3.3 3.6 CVDD 1.62 1.8 1.98 ...

Page 24

... Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Typical load capacitance Drive level Equivalent series resistance 24 XTI XTO XT1 C1 C2 Figure 12 - Crystal Oscillator Circuit Zarlink Semiconductor Inc. 20.4800MHz. ± 25ppm. ± 50ppm. 27pF 0.4mW max. <25 OSCMODE Data Sheet ...

Page 25

... Data Sheet 6.0 Application Circuit Figure 13 - Typical Application Circuit Zarlink Semiconductor Inc. MT352 25 ...

Page 26

... MT352 26 Zarlink Semiconductor Inc. Data Sheet ...

Page 27

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Page 28

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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