N87C51GB Intel Corporation, N87C51GB Datasheet

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N87C51GB

Manufacturer Part Number
N87C51GB
Description
CHMOS single-chip 8-bit microcontroller. 3.5 MHz to 12 MHz, 8 Kbytes OTP / 8 Kbytes internal program memory
Manufacturer
Intel Corporation
Datasheet

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MEMORY ORGANIZATION
PROGRAM MEMORY Up to 8 Kbytes of the program memory can reside in the on-chip ROM Also the device
can address up to 64K of program memory external to the chip
DATA MEMORY This microcontroller has a 256 x 8 on-chip RAM In addition it can address up to 64 Kbytes of
external data memory
The Intel 8XC51GB is a single-chip control oriented microcontroller which is fabricated on Intel’s CHMOS III-E
technology The 8XC51GB is an enhanced version of the 8XC51FA and uses the same powerful instruction
set and architecture as existing MCS 51 microcontroller products Added features make it an even more
powerful microcontroller for applications that require On-Chip A D Pulse Width Modulation High Speed I O
up down counting capabilities and memory protection features It also has a more versatile serial channel that
facilitates multi-processor communications
8 Kbytes On-Chip ROM OTP ROM
256 Bytes of On-Chip Data RAM
Two Programmable Counter Arrays
with
Three 16-Bit Timer Counters with
Dedicated Watchdog Timer
8-Bit 8-Channel A D with
Programmable Serial Channel with
Serial Expansion Port
Programmable Clock Out
Extended Temperature Range
(
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
b
Other brands and names are the property of their respective owners
2 x 5 High Speed Input Output
Channels Compare Capture
Pulse Width Modulators
Watchdog Timer Capabilities
Four Programmable Modes
Capture Baud Rate Generation
(Timer 2)
Eight 8-Bit Result Registers
Four Programmable Modes
Framing Error Detection
Automatic Address Recognition
40 C to
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
INTEL CORPORATION 1995
a
87C51GB 8 Kbytes OTP 8 Kbytes Internal Program Memory
83C51GB 8 Kbytes Factory Programmable ROM
80C51GB CPU with RAM and I O
8XC51GB 3 5 MHz to 12 MHz
8XC51GB-1 3 5 MHz to 16 MHz
85 C)
Commercial Express
8XC51GB
November 1994
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48 Programmable I O Lines with
40 Schmitt Trigger Inputs
15 Interrupt Sources with
Pre-Determined Port States on Reset
High Performance CHMOS Process
TTL and CHMOS Compatible Logic
Levels
Power Saving Modes
64K External Data Memory Space
64K External Program Memory Space
Three Level Program Lock System
ONCE (ON-Circuit Emulation) Mode
Quick Pulse Programming Algorithm
MCS 51 Microcontroller Fully
Compatible Instruction Set
Boolean Processor
Oscillator Fail Detect
Available in 68-Pin PLCC
7 External 8 Internal Sources
4 Programmable Priority Levels
CC
CC
Order Number 272337-002

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N87C51GB Summary of contents

Page 1

... Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 8XC51GB Commercial Express ...

Page 2

Figure 1 8XC51GB Block Diagram PROCESS INFORMATION This device is manufactured on P629 0 a CHMOS III-E process Additional process and reliability infor- mation is available in Intel’s Components Quality and Reliability Handbook Order No 210997 2 PACKAGES Part ...

Page 3

PARALLEL I O PORTS The 8XC51GB contains six 8-bit parallel I O ports All six ports are bidirectional and consist of a latch an output driver and an input buffer Many of the port pins have multiplexed I O and ...

Page 4

ALTERNATE PORT FUNCTIONS Ports and 5 have alternate functions as well as their I O function as described below Port Pin P0 0 ADO– AD7 T2EX P1 ...

Page 5

This pin also receives the 12 75V programming sup- ply voltage (V ) during programming (OTP only) PP XTAL1 Input to the inverting oscillator amplifier XTAL2 Output from the inverting oscillator amplifi CONVERTER The 8XC51GB A D ...

Page 6

for Crystals e g For Ceramic Resonators contact resonator manufacturer Figure 4 Oscillator Connections Figure 5 External Clock Drive Configuration IDLE MODE The user’s software can invoke the Idle Mode When the microcontroller ...

Page 7

... C The 87C51GB EXPRESS is packaged in a the 68-lead PLCC package In order to designate a part as an EXPRESS part a ‘‘T’’ is added as a prefix to the part number TN87C51GB denotes an EX- PRESS part in a PLCC package All AC and DC parameters in this data sheet apply to the EXPRESS devices ...

Page 8

ABSOLUTE MAXIMUM RATINGS Ambient Temperature under Bias Storage Temperature Voltage Pin per I O Pin OL Voltage on Any Other Pin ...

Page 9

DC CHARACTERISTICS (Over Operating Conditions) (Continued) Symbol Parameter V Output High Voltage OH (Ports and 5 ALE PSEN) V Output High Voltage OH1 (Port 0 in External Bus Mode) I Logical 0 Input Current IL (Ports ...

Page 10

I Max at other frequencies is given by CC Active Mode I Max (Osc Freq Idle Mode I Max (Osc Freq Where Osc Freq is in ...

Page 11

EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters The first char- acter is always a ‘‘T’’ (stands for time) The other characters depending on their positions stand for the name of a signal or the logical status ...

Page 12

EXTERNAL PROGRAM MEMORY READ CYCLE EXTERNAL DATA MEMORY READ CYCLE EXTERNAL DATA MEMORY WRITE CYCLE 12 272337 –11 272337 –12 272337 –13 ...

Page 13

SERIAL PORT TIMING SHIFT REGISTER MODE Test Conditions Over Operating Conditions Load Capacitance Symbol Parameter TXLXL Serial Port Clock Cycle Time TQVXH Output Data Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge TXHDX Input Data ...

Page 14

SEP AC TIMING SPECIFICATIONS Test Conditions Over Operating Conditions Load Capacitance Symbol Parameter TXSXL SEPCLK Cycle Time TXSST Output Data Setup to SEPCLK TXSOH Output Data Hold after SEPCLK TXSIH Input Data Hold after SEPCLK Sampling Edge TXSDV Input ...

Page 15

AC TESTING INPUT OUTPUT WAVEFORMS AC inputs during testing are driven ‘‘1’’ and 0 5V for a Logic ‘‘0’’ Timing measurements are made at V for a Logic ‘‘1’’ and V max for a Logic ‘‘0’’ IH ...

Page 16

A D CONVERTER SPECIFICATIONS Parameter Temperature Coefficients Offset Full Scale Differential Non-Linearity Input Capacitance Off Isolation Feedthrough V Power Supply Rejection CC Input Resistance to Sample-and-Hold Capacitor DC Input Leakage NOTES These values are expected for most parts at ...

Page 17

PROGRAMMING THE OTP The part must be running with a 4 MHz to 6 MHz oscillator The address of a location to be pro- grammed is applied to address lines while the code byte to be programmed in that location ...

Page 18

PROGRAMMING ALGORITHM Refer to Table 2 and Figures 11 and 12 for address data and control signals set up To program the 87C51GB the following sequence must be exer- cised 1 Input the valid address on the address lines ...

Page 19

ROM and EPROM Lock System The 87C51GB and the 83C51GB program lock sys- tems when programmed protect the on-board pro- gram against software piracy The 83C51GB has a one-level program lock system and a 64-byte encryption table See line 2 ...

Page 20

OTP PROGRAMMING AND VERIFICATION CHARACTERISTICS ( 20 Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current PP 1 TCLCL Oscillator Frequency TAVGL Address Setup ...

Page 21

A D Glossary of Terms Absolute Error The maximum difference between corresponding actual and ideal code transitions Ab- solute Error accounts for all deviations of an actual converter from an ideal converter Actual Characteristic The characteristic of an ac- tual ...

Page 22

Sample Window Begins when the sample capaci- tor is attached to a selected channel and ends when the sample capacitor is disconnected from the se- lected channel Successive Approximation conversion method which uses a binary search ...

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