SAA7346H Philips Semiconductors, SAA7346H Datasheet
SAA7346H
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SAA7346H Summary of contents
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... DATA SHEET SAA7346 Shock absorbing RAM addresser Preliminary specification File under Integrated Circuits, IC01 Philips Semiconductors INTEGRATED CIRCUITS July 1994 ...
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... T storage temperature stg ORDERING INFORMATION TYPE NUMBER PINS SAA7346H 44 Note 1. When using reflow soldering it is recommended that the Dry Packing instructions in the “Quality Reference Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011. July 1994 GENERAL DESCRIPTION The SAA7346 can be used to make a CD player insensitive to shocks ...
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... Philips Semiconductors Shock absorbing RAM addresser BLOCK DIAGRAM handbook, full pagewidth 14 RESET 8 TMS 16 SICL 15 SIDA 17 SILD V SS1 July 1994 DATA INPUT MULTIPLEXER SAA7346 ADDRESS MULTIPLEXER WRITE POINTER REGISTER MICROCONTROLLER MONITOR INTERFACE CONTROLLER SHOCK DETECTORS SS2 Fig.1 Simplified SAA7347 block diagram. 3 Preliminary specification ...
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... Philips Semiconductors Shock absorbing RAM addresser PINNING SYMBOL PIN CFLG 1 correction flag input from CD decoder KILL 2 kill input SCLI 3 multi-speed I WCI 4 multi-speed I SDI 5 multi-speed I CONFIG 6 external DRAM select input; HIGH 4 Mbit, LOW 1 Mbit CLKIN 7 16.9344 MHz system clock input TMS 8 test mode select input; active HIGH ...
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... Philips Semiconductors Shock absorbing RAM addresser SYMBOL PIN DRAM data bus inputs/outputs V 43 supply ground 2 SS2 V 44 supply voltage 2 DD2 handbook, full pagewidth CFLG KILL SCLI WCI SDI CONFIG CLKIN TMS OTD RCD2 SSD FUNCTIONAL DESCRIPTION input/output interfaces The SAA7346 contains an asynchronous serial input and a serial output interface ...
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... Philips Semiconductors Shock absorbing RAM addresser the position of the subcode-sync to the audio data. This signal determines the accuracy with which the SAA7346 sews audio data together after a shock. When the CD decoder preforms a jump the NSF will be missed. The PLL system will insert the missing pulse. The resulting signal is ...
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... Philips Semiconductors Shock absorbing RAM addresser handbook, full pagewidth (NSF + S_NSF) During normal operation the FIFO will fill up because writing is carried out twice as fast as reading; this is the fill mode. If the FIFO is full the monitor will detect and set the full flag. At the same time the fill flag will be reset thus preventing audio data from being written in to the FIFO ...
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... Philips Semiconductors Shock absorbing RAM addresser Table 2 Command register flag functions. COMMAND Flush Flush, when set, will empty the FIFO, reset the read and write pointer addresses. Then writing will resume to the FIFO. Flag reset automatically. Bypass Bypass, when set, will power down the SAA7346. The I The parallel interface port controls RAS, CAS, WE and OE which are pulled HIGH. KILL passes directly to KILLOUT. When exiting by-pass mode the FIFO is automatically fl ...
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... Philips Semiconductors Shock absorbing RAM addresser Table 3 Internal status signals. STATUS Lm and Lm1 The two Most Significant Bits (MSB) of the FIFO. These can be used to display the FIFO length or correct the subcode time information. The FIFO length is shown in Table 4. FRM_ER Framing error flag is set when: 1 ...
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... Philips Semiconductors Shock absorbing RAM addresser Read operation sequence: SILD is held LOW by the microcontroller. Status information is clocked from the internal status register on the LOW-to-HIGH clock transition of SICL. SICL and SILD are pulled HIGH by the microcontroller to indicate that communications have finished. DRAM interface ...
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... Philips Semiconductors Shock absorbing RAM addresser 2 Table 6 SAA7346 I S output speeds INPUT RCD2 SPEED (1) LOW CAV (2) LOW LOW LOW HIGH HIGH Notes 1. CAV with speed at outer edge of disc 1.5 at inner edge of disc build-up a delay, RCD2 should be made HIGH temporarily for twice the delay time. ...
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... Philips Semiconductors Shock absorbing RAM addresser SYMBOL PARAMETER I CLKIN NPUT f system clock frequency clk t system clock HIGH time H t system clock rise time r t system clock fall time CFLG, KILL, CONFIG NPUTS AND V LOW level input voltage IL V HIGH level input voltage ...
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... Philips Semiconductors Shock absorbing RAM addresser SYMBOL PARAMETER O KILLOUT; UTPUT OPEN DRAIN V LOW level output voltage OL I output current O C load capacitance L t output fall time D3; NPUTS OUTPUTS TO NORMAL V LOW level input voltage IL V HIGH level input voltage IH I input leakage current ...
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... Philips Semiconductors Shock absorbing RAM addresser SYMBOL PARAMETER .8) RANSMITTER SEE IG Clock output SCLO T clock cycle time cy t clock HIGH time H t clock LOW time L Outputs: SDO and WCO t delay time d t hold time h Microcontroller interface timing (see Figs 12 and 13 SICL SILD ...
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... Philips Semiconductors Shock absorbing RAM addresser SYMBOL PARAMETER DRAM interface timing (see Figs 14 and 15) T read or write cycle time cy t access time from CAS CAC t access time from OE OAC data input hold time h3 t RAS HIGH time RH t RAS LOW time ...
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... Philips Semiconductors Shock absorbing RAM addresser handbook, full pagewidth SCLI SDI WCI handbook, full pagewidth SCLO SDO WCO handbook, full pagewidth SCLI WCI LEFT CHANNEL SDI MSB Fig.10 Typical I July 1994 Fig input timing Fig output timing. 5.67 s LSB MSB 2 S data input waveform 4.2 MHz ...
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... Philips Semiconductors Shock absorbing RAM addresser handbook, full pagewidth SCLO WCO LEFT CHANNEL SDO MSB Fig.11 Typical handbook, full pagewidth SILD t d SICL SIDA July 1994 11.34 s LSB MSB 2 S data output waveform 2.1 MHz Fig.12 Microcontroller timing; READ mode. 17 Preliminary specification ...
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... Philips Semiconductors Shock absorbing RAM addresser handbook, full pagewidth SILD SICL SIDA July 1994 0 su1 V – 0 0.8 V Fig.13 Microcontroller timing; WRITE mode. 18 Preliminary specification – su2 – 0 MGB440 SAA7346 ...
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Acrobat reader. white to force landscape pages to be ... RAS t CRd t RCd CAS RAh t su1 A0 ROW ...
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... Philips Semiconductors Shock absorbing RAM addresser handbook, full pagewidth RAS t CRd t RCd CAS RAh t su1 A0 to ROW July 1994 CAh t su2 COLUMN t Wsu t Wh1 Wh2 t RWI t WCI t DRh Dsu OUTPUT Fig.15 WRITE cycle timing. 20 Preliminary specification SAA7346 – 0.8V DD 0.8 V ...
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... Philips Semiconductors Shock absorbing RAM addresser APPLICATION INFORMATION handbook, full pagewidth CFLG KILL bus from CD decoder 5 V 16.9 MHz CLKIN OTD RCD2 SSD July 1994 bit V DD DRAM CAS RAS OE 100 SAA7346 micro- controller 10 interface k S_NSF RSB RESET KILLOUT Fig.16 SAA7346 application diagram. ...
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... Philips Semiconductors Shock absorbing RAM addresser PACKAGE OUTLINE handbook, full pagewidth seating plane 44 1 pin 1 index 11 12 0.8 Dimensions in mm. Fig.17 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 July 1994 0.1 S 12.9 12 0.40 0. 0.20 10.1 9.9 1.85 1.65 0.25 ...
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... Philips Semiconductors Shock absorbing RAM addresser SOLDERING Plastic quad flat-packs B Y WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing ...
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... Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel ...