MACH111-10VC Lattice Semiconductor Corp., MACH111-10VC Datasheet
MACH111-10VC
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MACH111-10VC Summary of contents
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FEATURES High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages SpeedLocking™ – guaranteed fixed timing product terms Commercial 5/5.5/6/7.5/10/12/15-ns t Configurable macrocells — Programmable polarity — ...
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... MACH231 MACH231SP Notes Commercial Industrial 2. -5 speed grade for MACH111 (SP speed grade for MACH131(SP The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that includes JTAG-compatible in-system programming (ISP). These devices offer five different density- I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & ...
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... Table 3. MACH 1 and 2 Family Package and I/O Options Device 44-pin PLCC MACH111 X MACH111SP X MACH131 MACH131SP MACH211 X MACH211SP X MACH221 MACH221SP MACH231 MACH231SP Note: 1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call your local Lattice/Vantis sales offi ...
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... Together, the PAL blocks and switch matrix allow the logic designer to create large designs in a single device instead of using multiple devices. I/O Pins PAL Block I/O Pins PAL Block Note: 1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells. Device PAL Blocks MACH111(SP) 2 MACH131(SP) 4 MACH211(SP) 4 MACH221(SP) 8 MACH231(SP) 8 Figure 1. Overall Architecture of MACH 1 & ...
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... The product terms drive the logic allocator, which allocates the appropriate number of product terms to generate the function. Device Number of Inputs to PAL Block MACH111 MACH111SP MACH131 MACH131SP MACH211 Logic Allocator The logic allocator (Figure block within which different product terms are allocated to the appropriate macrocells in groups of four product terms called “ ...
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... Product Term Cluster Figure 2. Product Term Clusters and the Logic Allocator Table 5. Logic Allocation for MACH111(SP) Output Macrocell Table 6. Logic Allocation for MACH131(SP) Output Macrocell From n-2 n-1 n From From n+1 n+1 n+2 Logic *MACH 2 only Allocator Available Clusters Output Macrocell ...
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Table 7. Logic Allocation for MACH211(SP) and MACH231(SP) Macrocell Output Buried Available Clusters Table 8. Logic Allocation for MACH221(SP) Macrocell Output Buried Available Clusters ...
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The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback, and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell. This allows for buried combinatorial or ...
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From n Logic Allocator To Switch Matrix a. Combinatorial, active high From Logic Allocator CLK 0 AR CLK n To Switch Matrix c. D-type register, active high From Logic n AP Allocator T CLK 0 AR ...
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PAL-Block Asynchronous Preset Sum of Products From Logic IC Allocator CLK 0 CLK n PAL-Block Asynchronous Reset Switch Matrix From n Logic Allocator To Switch Matrix a. Combinatorial n From Logic Allocator CLK 0 CLK n To Switch Matrix c. ...
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... HIGH. Clock pins are also available as inputs, although care must be taken when a signal acts as both clock and input to the same device. Device Number of Clocks Available MACH111 MACH111SP MACH131 MACH131SP MACH211 All flip-flops have asynchronous reset and preset. This is controlled by the common product terms that control all fl ...
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Output Enable Product Terms (Common to bank of I/O Cells) SPEEDLOCKING FOR GUARANTEED FIXED TIMING The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, and even more importantly, guaranteed ...
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JTAG IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports. This ...
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V rise must be monotonic and the clock must be inactive until the reset CC delay time has elapsed. SECURITY BIT A security bit is provided on the MACH devices as a deterrent to unauthorized copying of ...
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... MACH111(SP) AND MACH131(SP) PAL BLOCK Switch Matrix for MACH111, MACH131, MACH131SP Output Enable Output Enable MACH 1 & 2 Families Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 Cell I/O Cell Output M Macro 1 Cell I/O Cell Output M Macro 2 Cell ...
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MACH211(SP) PAL BLOCK Switch Matrix MACH 1 ...
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MACH221(SP) PAL BLOCK Switch Matrix MACH 1 & ...
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MACH231(SP) PAL BLOCK Switch Matrix ...
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... BLOCK DIAGRAM (MACH111, MACH111SP CLK CLK CLK CLK Block A CLK I/O – I/O CLK I/O Cells 16 16 Macrocells AND Logic Array and Logic Allocator 26 Switch Matrix AND Logic Array and Logic Allocator Macrocells 16 16 I/O Cells 16 16 I/O – I Block B MACH 1 & 2 Families ...
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BLOCK DIAGRAM (MACH131, MACH131SP) Block A I/O – I I/O Cells 16 4 Macrocells AND Logic Array and Logic Allocator AND Logic Array and Logic Allocator OE Macrocells 4 ...
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BLOCK DIAGRAM (MACH211, MACH211SP) Block A I/O –I I/O Cells Macrocells Macrocells AND Logic Array and AND Logic Array and Logic Allocator OE 2 ...
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BLOCK DIAGRAM (MACH221, MACH221SP) 22 MACH 1 & 2 Families 14051K-011 ...
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BLOCK DIAGRAM (MACH231, MACH231SP) MACH 1 & 2 Families 14051K-012 23 ...
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... Output Short-Circuit Current SC Notes: 1. This applies to MACH111SP, MACH131SP, and die code “B” or later for MACH211(SP) and MACH231(SP). This does not apply to MACH111, MACH131, MACH221(SP), and die code “A” for MACH211(SP) and MACH231(SP). 2. Total I for one PAL block should not exceed 64 mA. ...
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... MACH111 AND MACH111SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Parameter Description Symbol t Input, I/O, or Feedback to Combinatorial Output PD Setup Time from Input, I/O, or Feedback Clock t Register Data Hold Time H t Clock to Output Clock Width t WH External 1/( Feedback Maximum f MAX Frequency Internal Feedback (f ...
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MACH131 AND MACH131SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Parameter Description Symbol t Input, I/O, or Feedback to Combinatorial Output PD t Setup Time from Input, I/O, or Feedback S t Hold Time H t Clock to Output CO t ...
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MACH211 AND MACH211SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Input, I/O, or Feedback to Combinatorial t PD Output Setup Time from Input, I/O, or Feedback Clock t Register Data Hold Time H t Clock ...
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MACH211 AND MACH211SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description Asynchronous Reset to Registered or Latched t AR Output t Asynchronous Reset Width (Note 2) ARW t Asynchronous Reset Recovery Time (Note 2) ARR Asynchronous Preset to ...
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MACH221 and MACH221SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description t Input, I/O, or Feedback to Combinatorial Output PD Setup Time from Input, I/O, or Feedback Clock t Register Data Hold Time H t Clock ...
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MACH221 and MACH221SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description t Asynchronous Preset Width (Note 3) APW t Asynchronous Preset Recovery Time (Note 3) APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, ...
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MACH231 AND MACH231SP SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description t Input, I/O, or Feedback to Combinatorial Output PD Setup Time from Input, I/O, or Feedback Clock t Register Data Hold Time H t Clock ...
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MACH231 AND MACH231SP (CONTINUED) SWITCHING CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol Parameter Description t Input Latch Gate Width LOW WIGL Input, I/O, or Feedback to Output Through t PDLL Transparent Input and Output Latches Asynchronous Reset to Registered or Latched ...
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... These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. MACH111(SP) 150 125 100 ...
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... Device Parameter Symbol MACH111(SP) MACH211(SP) MACH221(SP) MACH131(SP) MACH231SP MACH231 MACH111(SP) MACH211(SP) MACH221(SP) MACH131(SP) MACH231SP MACH231 34 Table 12 Parameter Description Supply Current (Static Supply Current (Active) MACH 1 & 2 Families Test Description Typ Unit 5V 25° MHz 80 135 5V 25° MHz 100 150 ...
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... Top View I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 Block A GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC Note: 1. Pin designators in parentheses ( ) apply to the MACH111SP 44-Pin PLCC TDI = Test Data In ...
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... MACH111SP-5/7/10/12/15) Top View I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 Block A GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC Note: 1. Pin designators in parentheses ( ) apply to the MACH111SP 36 MACH111-5/7/10/12/15 AND ( 44-Pin TQFP ...
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PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15) Top View Block I/O8 I/O9 13 I/O10 14 I/O11 15 I/O12 16 I/O13 17 I/O14 18 I/O15 19 CLK0/I0 20 VCC 21 GND 22 CLK1/I1 23 I/O16 24 I/O17 25 I/O18 ...
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PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15) Top View Block A 1 GND GND 2 TDI I/ I/O9 7 I/O10 I/O11 8 9 I/O12 10 I/O13 11 I/O14 12 I/O15 13 IO/CLK0 ...
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TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15) Top View Block A TDI 1 I/5 2 I/O8 3 I/O9 4 I/O10 5 I/O11 6 I/O12 7 I/O13 8 I/O14 9 I/O15 10 I0/CLK0 GND 13 GND 14 I1/CLK1 15 ...
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PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15) Top View Block A I/O5 I/O6 I/O7 (TDI (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 Block B PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I ...
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TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND MACH211SP-6/7/10/12/15) Top View Block A I/O5 I/O6 I/O7 (TDI) I0 (CLK 0/I0) CLK0/I1 GND (TCK) CLK1/I2 I/O8 I/O9 I/O10 I/O11 Block B PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = ...
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PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15) Top View I/O7 I/O8 I/O9 I/O10 I/O11 CLK0/I0 CLK1/I1 I2 VCC GND I3 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output ...
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PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15) Top View 1 GND GND 2 TDI N N/C 8 I/O7 9 I/O8 I/ I/O10 12 I/O11 13 IO/CLK0 GND ...
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PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15) Top View I/O8 13 I/O9 I/O10 14 I/O11 15 16 I/O12 17 I/O13 18 I/O14 I/O15 19 CLK GND CLK ...
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PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15) Top View 1 GND GND 2 TDI I/ I/O10 8 I/O11 9 I/O12 I/O13 10 11 I/O14 12 I/O15 13 IO/CLK0 GND ...
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TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15) Top View TDI I/O8 3 I/O9 4 I/O10 5 I/O11 6 I/O12 7 I/O13 8 I/O14 9 I/O15 10 I0/CLK0 GND 13 GND 14 I1/CLK1 15 I/O16 16 ...
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... Note: 1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e. MACH131SP-5YC-7YI MACH 131 Valid Combinations – Industrial MACH111 JC, VC JC, VC MACH111SP MACH131 JC/1 MACH131SP VC, YC MACH211 JC, VC MACH211SP JC, VC MACH221 JC MACH221SP YC MACH231 ...
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MACH 1 & 2 Families ...