HL14203 Hynix Semiconductor, HL14203 Datasheet
HL14203
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HL14203 Summary of contents
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... LCD Driver IC Preliminary 2Q. 1999 Hyundai Electronics Industries System IC Division 1 HL14203 ...
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... Contents 1. General Description 2. Features 3. Block Diagram 4. Pin Diagram 5. Pin Description 6. Serial I/O Data Format 7. Registers 8. Key Scan Function 9. LCD Function 10. Power On Reset 11. Power Down Mode 12. Oscillator Port 13. Electrical Characteristics 14. Application 2 HL14203 ...
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... General Description The HL14203 is 1/3 duty LCD display driver. It can drive directly maximum 126 segments. Also it has four general purpose output ports and a key scan function that accepts input from keys. 2. Features • LCD display ..................................... 42 segments x 3 commons • Key scan ............................................ Maximum 30 keys • ...
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... Block Diagram COMMOM DRIVER LCD VCL1 BIAS VCL2 VDD SVD VSS CLOCK OSC GENERATOR TEST TEST CONTROL SEGMENT DRIVER LCD DISPLAY & CONTROL REGISTER RESET SERIAL I/O CLOCK KEY SCAN 4 HL14203 SI SO SCK ...
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... Pin Diagram KS6 KIN1 KIN2 KIN3 KIN4 KIN5 TEST VDD VCL1 VCL2 VSS OSC SO CE SCK HL14203 HL14203 32 SEG32 31 SEG31 30 SEG30 29 SEG29 28 SEG28 27 SEG27 26 SEG26 25 SEG25 24 SEG24 23 SEG23 22 SEG22 21 SEG21 20 SEG20 19 SEG19 18 SEG18 17 SEG17 ...
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... Key Scan Input Pins 1 Serial I/O Control Pin 1 Serial I/O Clock Pin 1 Serial I/O Data Output Pin 1 Serial I/O Data Input Pin 1 Test Pin. “1” Test mode , “0” Normal Mode 4 Output Port share SEG[4:1] 1 Power Supply Pin 1 Ground Pin 6 HL14203 Contents ...
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... Serial I/O Data Format 1) Writing Mode i )SCK is stopped at the low level CE SCK SCK SCK D41 D42 Display data D43 D44 D45 D83 D84 Display data D85 D86 D87 D125 D126 Display data 7 HL14203 Control data Fixed data Fixed data ...
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... Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data D41 D42 Display data 1 0 D44 D45 D43 D83 D84 Display data 1 0 D85 D86 D87 D125 D126 Display data 8 HL14203 Control data Fixed data Fixed data ...
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... Reading Mode i ) SCK is stopped at the low level CE SCK SCK is stopped at the high level CE SCK 43H address K30 ~ K1 : Key data SA : Sleep acknowledge Output data 9 HL14203 K10 K11 K12 SA K29 K30 Output data X : don’t care XX K10 K11 K12 SA K29 K30 X : don’t care ...
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... D95 D97 D98 D100 D101 D103 D104 D106 D107 D109 D110 D112 D113 D115 D116 D118 D119 D121 D122 D124 D125 10 HL14203 COM3 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 ...
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... Stopped 1 0 Sleep Stopped 1 1 Sleep Stopped Maximum number of Input Pins KS2 KS2 SEG42 Output Pin Status SEG2/ P2 SEG3/ P3 SEG2 SEG3 P2 SEG3 OSC SEG / COMMON Output KS1 KS2 Operating HL14203 SEG4/ P4 SEG4 SEG4 SEG4 P4 Output Pin Status KS3 KS4 KS5 KS6 ...
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... ADDRESS 43H KIN1 KS1 / SEG41 K1 KS2 / SEG42 K6 KS3 K11 KS4 K16 KS5 K21 KS6 K26 On Off Read Data K1 ~ K30, SA KIN1 KIN1 KIN1 K12 K13 K14 K17 K18 K19 K22 K23 K24 K27 K28 K29 12 HL14203 KIN1 K5 K10 K15 K20 K25 K30 ...
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... Multiple key presses are recognized by determining whether multiple key data bits are set. • key is pressed for longer than 800T ( where T=1/fosc ) the HL14203 outputs a key data read request (a low level on SO pin) to the controller. The controller acknowledges this request and reads the key data. However high during a serial data transfer, SO will be set high. • ...
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... Keys are scanned until all keys are released. Multiple key pre- sses are recognized by determining whether multiple key data bits are set. • key is pressed for longer than 800T ( where T=1/fosc ) the HL14203 outputs a key data read request (a low level on SO) to the controller. The controller acknowledges this request and reads the key data ...
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... Key data read request Multiple Key Presses Although the HL14203 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or mult- iple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed ...
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... COM2 only SEG1 ~ SEG42 “On” at COM3 only SEG1 ~ SEG42 “On” at COM1 and COM2 SEG1 ~ SEG42 “On” at COM1 and COM3 SEG1 ~ SEG42 “On” at COM2 and COM3 16 HL14203 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 VDD VCL1,VCL2 ...
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... COM2 only SEG1 ~ SEG42 “On” at COM3 only SEG1 ~ SEG42 “On” at COM1 and COM2 SEG1 ~ SEG42 “On” at COM1 and COM3 SEG1 ~ SEG42 “On” at COM2 and COM3 17 HL14203 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 VDD VCL1 ...
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... Reset is applied and the display is turned off but display data is not cleared. • Key scan Reset is applied and all the key data is set to low. Display and control data transfer Undefined System reset period Power supply voltage Vdd rise time : t1 > 1ms Power supply voltage Vdd fall time : t2 > 1ms 18 HL14203 SVD t2 Defined ...
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... This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode. : Low *) : Low : Low : Low *) : X : High : High 19 HL14203 ...
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... Oscillator Port OSC Pin Diagram OSC Oscillator circuit consists of internal R and C. No Capacitor OSC Open HL14203 has internal resistor and capacitor can be oscillation without external capacitor. If you want to adjust the clock period then you can adjust it using external capacitor Using Capacitor OSC C ...
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... SCK,SI tdh SCK,SI tcp CE,SCK tcs CE,SCK tch CE,SCK t0H SCK toL SCK tr CE,SCK,SI tf CE,SCK,SI SO,RPU = 4.7k , tdc CL = 10pF*1 SO,RPU = 4.7k , tdr CL = 10pF*1 21 HL14203 Rating unit -0.3 to +7.0 V -0.3 to +7.0 V -0.3 to VDD+0.3 V -0.3 to +7.0 V -0.3 to VDD+0.3 V 300 200 mW ¡ É -40 to +85 ¡ ...
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... COM to COM3 : 1/3 bias, VMID5 Io = ¡ ¾ 1 00µA fOSC OSC : C = TBD IDD1 Sleep mode VDD = 6.0V, output open, IDD2 1/2 bias,fOSC = 38 KHz VDD = 6.0V, output open, IDD3 1/3 bias,fOSC = 38 KHz 22 HL14203 min typ max O.1VDD TBD 2.5 TBD 5.0 -5.0 0.05VDD 50 100 250 6 ...
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... Timing diagram of SIO CE t0H SCK tr SI tds tdh SO VIH1 CE SCK tcp SI SO t0L tf tcs tdc 23 HL14203 VIL tch tdr ...
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... Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded ...
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... Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded ...
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... Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL14203 is reset by the SVD. *2). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded ...