MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 141
142
Page 142
143
Page 143
144
Page 144
145
Page 145
146
Page 146
147
Page 147
148
Page 148
149
Page 149
150
Page 150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
Page 142/222:

Serial Peripheral Interface (SPI)

Download datasheet (3Mb)Embed
PrevNext
Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI)

Addr.
Register Name
SPI Control Register
$000A
(SPCR)
See page 149.
SPI Status Register
$000B
(SPSR)
See page 151.
SPI Data Register
$000C
(SPDR)
See page 149.
Figure 11-2. SPI I/O Register Summary
11.4 Operation
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
Technical Data
142
Bit 7
6
5
Read:
SPIE
SPE
Write:
Reset:
0
0
Read:
SPIF
WCOL
MODF
Write:
Reset:
0
0
Read:
Bit 7
Bit 6
Bit 5
Write:
Reset:
= Unimplemented
U = Unaffected

Serial Peripheral Interface (SPI)

For More Information On This Product,
Go to: www.freescale.com
4
3
2
1
MSTR
CPOL
CPHA
SPR1
0
U
U
U
0
Bit 4
Bit 3
BIt 2
Bit 1
Unaffected by reset
MC68HC705C8A — Rev. 3
Bit 0
SPR0
U
Bit 0