MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


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Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram
11.6 Serial Clock Polarity and Phase
To accommodate the different serial communication requirements of
peripheral devices, software can change the phase and polarity of the
SPI serial clock. The clock polarity bit (CPOL) and the clock phase bit
(CPHA), both in the SPCR, control the timing relationship between the
serial clock and the transmitted data.
and CPHA bits affect the clock/data timing.
SS
CPHA
CPOL
0
0
SCK (A)
1
0
SCK (B)
0
1
SCK (C)
1
1
SCK (D)
SDO/SDI
MSB
CAPTURE STROBE
Technical Data
146
MASTER/SLAVE
MCU 1
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1
I/O
PORT
2
3
SLAVE MCU 2
SLAVE MCU 1
BIT 6
BIT 5
BIT 4
BIT 3
Figure 11-6. SPI Clock/Data Timing
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
MASTER/SLAVE
MCU 2
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
0
1
I/O
PORT
2
3
SLAVE MCU 0
Figure 11-6
shows how the CPOL
BIT 2
BIT 1
LSB
MC68HC705C8A — Rev. 3