MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


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Page 147/222:

SPI Error Conditions

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Freescale Semiconductor, Inc.
11.7 SPI Error Conditions
These conditions produce SPI system errors:
11.7.1 Mode Fault Error
A mode fault error results when a logic 0 occurs on the PD5/SS pin of a
master SPI. The MCU takes these actions when a mode fault error
occurs:
11.7.2 Write Collision Error
Writing to the SPDR during a transmission causes a write collision error
and sets the WCOL bit in the SPSR. Either a master SPI or a slave SPI
can generate a write collision error.
MC68HC705C8A — Rev. 3
MOTOROLA
For More Information On This Product,
Bus contention caused by multiple master SPIs (mode fault error)
Writing to the SPDR during a transmission (write-collision error)
Failing to read the SPDR before the next incoming byte sets the
SPIF bit (overrun error)
Puts the SPI in slave mode by clearing the MSTR bit
Disables the SPI by clearing the SPE bit
Sets the MODF bit
Master — A master SPI can cause a write collision error by writing
to the SPDR while the previously written byte is still being shifted
out to the PD3/MOSI pin. The error does not affect the
transmission of the previously written byte, but the byte that
caused the error is lost.
Slave — A slave SPI can cause a write collision error in either of
two ways, depending on the state of the CPHA bit:
– CPHA = 0 — A slave SPI can cause a write collision error by
writing to the SPDR while the PD5/SS pin is at logic 0. The
error does not affect the byte in the SPDR, but the byte that
caused the error is lost.
Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)

SPI Error Conditions

Technical Data