MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Page 61
62
Page 62
63
Page 63
64
Page 64
65
Page 65
66
Page 66
67
Page 67
68
Page 68
69
Page 69
70
Page 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
Page 67/222

Download datasheet (3Mb)Embed
PrevNext
Freescale Semiconductor, Inc.
2. COP clear bit (COPC) at address $1FF0
NOTE:
The non-programmable watchdog COP is disabled in bootloader mode,
even if the NCOPE bit is programmed.
Figure 5-4
NON-PROGRAMMABLE COP WATCHDOG (MC68HC05C4A TYPE)
5.3.4 Clock Monitor Reset
When the CME bit in the COP control register is set, the clock monitor
detects the absence of the internal bus clock for a certain period of time.
The timeout period depends on processing parameters and varies from
5 s to 100 s, which implies that systems using a bus clock rate of
200 kHz or less should not use the clock monitor function.
If a slow or absent clock is detected, the clock monitor causes a system
reset. The reset is issued to the external system for four bus cycles using
the bidirectional RESET pin.
Special consideration is required when using the STOP instruction with
the clock monitor. Since STOP causes the system clocks to halt, the
clock monitor issues a system reset when STOP is executed.
MC68HC705C8A — Rev. 3
MOTOROLA
For More Information On This Product,
To clear the non-programmable COP watchdog and start a new
COP timeout period, write a logic 0 to bit 0 of address $1FF0.
Reading address $1FF0 returns the mask option register 1
(MOR1) data at that location. See
is a diagram of the non-programmable COP.
2
2
2
2
2
2
2
2
2
2
2
Figure 5-4. Non-Programmable COP Watchdog Diagram
Resets
Go to: www.freescale.com
Resets
Reset Sources
9.5.2 Mask Option Register
NCOPE
2
2
2
2
2
2
Technical Data
1.