MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


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Page 80/222:

Parallel Input/Output (I/O)

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Freescale Semiconductor, Inc.

Parallel Input/Output (I/O)

7.3.3 Port A Logic
Figure 7-3
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit.
Table 7-1
DDRA Bit
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
NOTE:
To avoid excessive current draw, tie all unused input pins to V
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
Technical Data
80
is a diagram of the port A I/O logic.
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
RESET
BIT DDRAx
PORT A DATA
WRITE $0000
REGISTER
BIT PAx
READ $0000
Figure 7-3. Port A I/O Logic
summarizes the operation of the port A pins.
Table 7-1. Port A Pin Functions
Accesses to DDRA
I/O Pin Mode
Read/Write
(1)
0
DDRA7–DDRA0
Input, Hi-Z
1
Output
DDRA7–DDRA0

Parallel Input/Output (I/O)

For More Information On This Product,
Go to: www.freescale.com
PAx
Accesses to PORTA
Read
Write
(2)
Pin
PA7–PA0
PA7–PA0
PA7–PA0
or V
,
DD
SS
MC68HC705C8A — Rev. 3