VT6102 BI Technologies, VT6102 Datasheet
VT6102
Available stocks
Related parts for VT6102
VT6102 Summary of contents
Page 1
... VIA Technologies, Inc. PCI F AST W ITH DATA SHEET VIA TECHNOLOGIES, INC. Ver_01 VT6102 E C THERNET ONTROLLER ACPI F UNCTION (Preliminary) DATE : August 1, 1999 Preliminary VT6102 1 ...
Page 2
... Via Technologies Incorporated. The VT6102 may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies ...
Page 3
... NTERNAL EGISTER 4-2-1. VT6102 internal register description (00-07H) ....................................21 4-2-2.VT6102 internal register description (08-09H) ....................................22 4-2-3. VT6102 internal register description (0C-1FH) ...................................23 4-2-4. VT6102 internal register description (20-2FH)....................................24 4-2-5. VT6102 internal register description (40-4FH)....................................25 4-2-6. VT6102 internal register description (6C-6FH) ...................................26 4-2-7. VT6102 internal register description (70-77H) ....................................27 4-2-8 ...
Page 4
... MII TX......................................................................40 6-3-2. MII MDIO ...................................................................40 ......................................................................41 6- OOT OM 6-4-1. One Dword bootrom access timing (with delay transaction) ........................41 6-4-2. One Dword bootrom access timing (without delay transaction) .....................42 6-4-3. Embedded Flash Cycle Timing.................................................43 7. APPLICATION SCHEMATIC ................................................... 45 8. PACKAGE MECHANICAL SPECIFICATIONS ..................................... 47 Ver_01 ........................................................32 Preliminary VT6102 4 ...
Page 5
... VIA Technologies, Inc. 1 Overview . 1-1. VT6102 PCI F E AST THERNET • Single chip Fast Ethernet MAC controller for PCI bus interface -- Compliant to PCI 2.2 specification. -- Provides a direct connection to PCI bus -- Supports two network ports : 10/100MB MII interface • High performance PCI mastering structure ...
Page 6
... PCIRST# PCICLK 115 VSS VDD GNT# REQ# AD31 AD30 120 AD29 AD28 VDD VSS AD27 125 AD26 AD25 128 AD24 1 5 Ver_01 VT6102 Preliminary VT6102 MA3 MA2 MA1 MA0 MD7 MD6 MD5 VSS VDD MD4 MD3 MD2/ECK MD1/EDI MD0/EDO BPCS BPRD# ...
Page 7
... I/O MD6 59 I/O MD5 58 I/O MD4 55 I/O MD3 54 I/O MD2/ECK 53 I/O MD1/EDI 52 I/O MD0/EDO 51 I/O MCRS 84 I MCOL 85 I Preliminary VT6102 Pin Name Pin Type MTXD3 88 O MTXD2 89 O MTXD1 90 O MTXD0 91 O MTXE 92 O MTXC 93 I MERR 94 I MRXC 97 I MRXDV ...
Page 8
... Input Input is a standard input-only signal. O Output This is a standard active driver. I/O Input / Output Thiis is an input/output signal T/S Tri-State Tri-stae is a bi-directional, Tri-stae input/output pin O/D Open Drain This allows multiple devices to share as a wire-OR Ver_01 Preliminary VT6102 Definition 8 ...
Page 9
... For data phases PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. I Bus grant asserts to indicate to the VT6102 that access to the bus is granted. O Bus request is asserted by the bus master indicate to the bus arbiter that it wants to use the bus ...
Page 10
... Serial ROM Data output Bootrom data bus 1 O Serial ROM Data input Bootrom data bus 2 O Serial ROM Clock signal Bootrom data bus [3-7] O Bootrom address line [15-0] Preliminary VT6102 Description data be synchronized Description the Boot ROM on the memory support data to 10 ...
Page 11
... VTEST, When VTEST=0,PHY reset high active, When VTEST=1,PHY reset low active. I Test control Pin,it can control PHY reset output polarity P VCC Power: +3.3V P Standby VCC Power: +3.3V G Ground Ground Memory Interface Power G Memory Interface Ground Preliminary VT6102 Description Description 11 ...
Page 12
... The VT6102 enhanced the FIFO management logic to handle received data packets up to four packets before transfer to system data buffer. This ability reduce the packets losing due to PCI bus mastering abrition latency. ...
Page 13
... CHKSUM 3-3-1. Direct Programming of EEPROM The VT6102 features a easy way to program external EEPROM in-situ. When the RESET is active and if the upper byte of 0FH on EEPROM is not 73H, the EEPR bit will not be set to indicate that the current EEPROM has not been programmed yet. This will allow the VT6102 to enter Direct Programming mode if EELOAD is also set. In this mode the user can directly control the EEPROM interface signals by writing to the ECSR Port and the value on the EECS, ESK and EDI bits will be driven onto the EECS, SK(MD2), and DI(MD1) outputs respectively ...
Page 14
... DISABLE_INTERRUPTS, ENABLE_INTERRUPTS, READ, WRITE, WAIT DISABLE_INTERRUPTS ( ); value = READ (CONFIG_B); value = value | EELOAD; WRITE (CONFIG_B, value); READ (CONFIG_B); WRITE (CONFIG_B, config_for_A); WRITE (CONFIG_B, config_for_B); WRITE (CONFIG_B, config_for_C); while (value || EELOAD) { value = READ (CONFIG_B); WAIT ( ); } ENABLE_INTERRUPTS ( ); } Ver_01 EEPROM Preliminary VT6102 14 ...
Page 15
... Multiple Chained buffer structure The VT6102 can support multiple chain buffer for direct map to OS`s data buffer. The VT6102 bus mastering module will direct move the data from network to the OS`s data buffer or direct transmit the data in OS`s buffer onto network not necessary move to a temperate data buffer. But the data buffer must be double word aligned. In this multiple chained buffer structure, the first data buffer’ ...
Page 16
... Simple Ring Buffer Structure 3-5-2 Interrupt Control The VT6102 can controllable the receive descriptors and transmit descriptor for what the interrupt occurred. The IC bit (DES1[23]) be set 1, the receive or transmit interrupt will be generate the interrupt no matter the frame been complete received or transmitted. This feature will enable the OS pre-fetch the frame header or saving the interrupt service overload ...
Page 17
... The VT6102 support flow control in both half duplex and full duplex. In half duplex mode, VT6102 support jam based flow control, when traffic busy, MAC will send jam pattern. In full duplex mode, the pause frame detection logic operate base on the flow control register 0x80, if this flow control bit is set to enable, The Vt6102 will detect PAUSE frame. ...
Page 18
... Base Address Registers Card Bus CIS Pointer(00) Expansion ROM Base Address Reserved Reserved Min_Gnt Interrupt Pin Next Item Ptr Power Management Control/Status Register Rserved Reserved Rserved Description Preliminary VT6102 0 Vendor ID (1106) Command Revision ID Cache Size SUB-Vendor ID Cap_Ptr Interrupt Line Capability ID (PMCSR) Rserved Reserved ...
Page 19
... Bit11 XXXX1b – PME# can be asserted from D0 Bit12 XXX1Xb – PME# can be asserted from D1 Bit13 XX1XXb – PME# can be asserted from D2 Bit14 X1XXXb – PME# can be asserted from D3h Bit15 1XXXXb – PME# can be asserted from D3c Refer to Power Management spec 1.0 Preliminary VT6102 Default ACC ...
Page 20
... VIA Technologies, Inc. 4-2. VT6102 I R NTERNAL EGISTER PAR3 TCR Reserved IMR1 MAR3 MAR7 GFSTATUS CURR [8:0] BCR1 MII DATA REG DEBUG1 CFGD Tally Counter_CRC STICKHW Reserved BPMD EE_CHKSUM 0 0000_00_0_pauseSR SOFT_TIMER_1 WOLCG.SET WOLCG.CLR Ver_01 M AP PAR2 PAR1 RCR PAR5 Reserved CR1 ...
Page 21
... VIA Technologies, Inc. 4-2-1. VT6102 internal register description (00-07H) OFFSET Bit Symbol 0-5H 0-63 PAR0-5 Ethernet address 06H 0 SEP 1 AR 06H 06H 06H 06H 4 PROM 5 RRFT0 06H 06H 6 RRFT1 06H 7 RRFT2 07H 0 RESV 07H 1 LB0 07H 2 LB1 07H 3 OFSET 07H 4 RESV ...
Page 22
... VIA Technologies, Inc. 4-2-2.VT6102 internal register description (08-09H) OFFSET Bit Symbol 08H 0 INIT 08H 1 STRT 08H 2 STOP 08H 3 RXON 08H 4 TXON 08H 5 TDMD 08H 6 RDMD 08H 7 RESV 09H 0 EREN 09H 1 RESV 09H 2 FDX 09H 3 DPOLL Disable TD/RD auto polling 09H 4 RESV ...
Page 23
... VIA Technologies, Inc. 4-2-3. VT6102 internal register description (0C-1FH) OFFSET Bit Symbol 0CH 0 PRX 0CH 1 PTX 0CH 2 RXE 0CH 3 TXE 0CH 4 TU 0CH 5 RU 0CH 6 BE 0CH 7 CNT 0DH 0 ERI 0DH 1 UDFI 0DH 2 OVFI 0DH 3 PKT Race FIFO overflow condition, it’s mean next packet race with ...
Page 24
... VIA Technologies, Inc. 4-2-4. VT6102 internal register description (20-2FH Length [10:0] Reserved RX DATA BUFFER START ADDRESS OFFSET Bit Symbol 20H 0 RERR 20H 1 CRC 20H 2 FAE 20H 3 FOV 20H 4 LONG 20H 5 RUNT 20H 6 SERR 20H 7 BUFF 21H 8 EDP 9 STP 10 CHN 11 PHY 12 BAR ...
Page 25
... VIA Technologies, Inc. 4-2-5. VT6102 internal register description (40-4FH) Reserved O Reserved TX DATA BUFFER START ADDRESS OFFSET Bit Symbol 40H 0-3 NCR0-3 Collision retry count 4 COLS 5 RESV 6 RESV 7 CDH 41H 8 ABT 9 OWC 10 CRS 11 UDF 12 TBUFF Invalid TD format or structure or TD underflow 13 SERR 14 RESV ...
Page 26
... VIA Technologies, Inc. 4-2-6. VT6102 internal register description (6C-6FH) OFFSET Bit Symbol 6CH 0-4 PHYAD Extend PHY device address 6CH 5 MFDC Accelerate MDC speed 6CH 6 MPO0 6CH 7 MPO1 6DH 0 SPD10 PHY Speed 6DH 1 LNKFL 6DH 2 RESV 6DH 3 MIIERR PHY device received error. ...
Page 27
... VIA Technologies, Inc. 4-2-7. VT6102 internal register description (70-77H) OFFSET Bit Symbol 70H 0 MDC 70H 1 MDI 70H 2 MDO 70H 3 MOUT MDIO out put enable indicator. 70H 4 MDPM Direct PHY programming mode enable 70H 5 WCMD Write enable to write PHY, reset while write complete ...
Page 28
... VIA Technologies, Inc. 4-2-8. VT6102 internal register description (78-7BH) OFFSET Bit Symbol 78H 0-5 RESV 78H 6 MIIOPT If MIIOPT=0,without extension clock. 78H 7 EELOAD Enable EEPROM embedded and direct programming , 79H 0 LATMEN Latency timer 79H 1 MWAIT Master write insert one wait state 2-2-2-2 ...
Page 29
... Sticky DS1_shadow, R/W by software Reserved jumper strapping MD5. MISR Suspend well MII polling status change interrupt. User defined, host driven interrupt Power event report in test mode Reserved MIMR Reserved diagnosis use mask User defined, host driven interrupt mask Reserved Reserved Preliminary VT6102 ...
Page 30
... VIA Technologies, Inc. 4-2-10. VT6102 internal register description (8C-A7H) OFFSET Bit Symbol 8C-8DH 0-15 BPMA Flash address port [15:0] 8EH 0-7 RESV 8FH 0-7 BPMD Flash write data output port 90H 0 EBPRD BOOTROM embedded read command 90H 1 EBPWR BOOTROM embedded write command ...
Page 31
... VIA Technologies, Inc. 4-2-11. VT6102 internal register description (B0-FFH) OFFSET Bit Symbol B0-B3H 0-31 CRC0 B4-B7H 0-31 CRC1 B8-BBH 0-31 CRC2 BC-BFH 0-31 CRC3 C0-CFH 0-127 Bytemsk BYTEMSK 0 D0-DFH 0-127 Bytemsk BYTEMSK 1 E0-EFH 0-127 Bytemsk BYTEMSK 2 F0-FFH 0-127 Bytemsk BYTEMSK 3 Ver_01 ...
Page 32
... 2500 Volts Min Max Unit - 100 -0.5 0.8 V 2.0 Vcc+.05 V -1.0 +1 0 Vcc-0 0.5 V -10 +10 uA Preliminary VT6102 Condition X1=25Mhz, V switching IN X1=25Mhz, V =Vcc or GND IN X1 undriven, V =Vcc or Undriven IN GND<V <Vcc 20uA -20uA 20uA -20uA 24uA OL GND<V <Vcc OUT 32 ...
Page 33
... Parameter Preliminary VT6102 @+ t fhold @$. t irhold Width (ns) Note (7.2, 10.6, 18.7) min:( 7.7, 11.1, 20.0), max:( 8.6, 12.7, 22.3) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.2) ( 6.9, 10.2, 18.0) ( 3.2, 4.8, 8. ...
Page 34
... Parameter Preliminary VT6102 @+ t fhold @$. T irhold Width (ns) Note (7.2, 10.6, 18.7) min:( 7.7, 11.1, 20.0), max:( 8.6, 12.7, 22.3) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.2) ( 7.0, 10.3, 18.2) ( 3.2, 4.8, 8. ...
Page 35
... T Parameter Preliminary VT6102 t dahold irhold Width (ns) Note ( 7.2, 10.6, 18.7) ( 7.7, 11.4, 20.0) ( 4.7, 7.0, 12.2) ( 4.7, 7.0, 12.3) ( 5.7, 8.4, 14.8) ( 7.2, 10.6, 18.7) ( 5.7, 8.4, 14.8) (5.2, 7.6, 13.4) ( 3.2, 4.8, 8.4) ...
Page 36
... IRDY# hold time tadval PCICLK rising edge to AD[31:0] Valid Delay tcbeval PCICLK rising edge to CBE[3:0] Valid Delay Note : 1.(xxx, xxx, xxx) : (best, normal, worst) Ver_01 @\+ @+ tirh0 Parameter Preliminary VT6102 @\; tirval tirh1 @\; tfh Width (ns) Note ( 7.2, 10.6, 18.7) ( 6.9, 10.2, 17.9) ( 4.7, 7.0, 12. ...
Page 37
... Note : 1.(xxx, xxx, xxx) : (best, normal, worst) Ver_01 @; \\\\\@\; tdah0 \\\\\@\; @$. \\\@ $. t tirh0 @+ @+ tdah1 Parameter Preliminary VT6102 tfh tirval1 irh1 @+ tdaval1 tdah2 Width (ns) Note ( 7.2, 10.6, 18.7) Min.( 6.8, 9.9, 17.5) Max( 7.6, 11.2, 19.7) ( 4.7, 7.0, 12.3) ( 5.3, 7.9, 13.8) Min( 7.7, 11.4, 20.0) Max( 9 ...
Page 38
... TRDY# hold time Note : 1.(xxx, xxx, xxx) : (best, normal, worst read only Ver_01 ccccccccccccc hfrhhhhhhhhhh znondddddozzz znxddddddozzz hhfllllllkhhh hhhhhhhhfrhhh \\@+ t daval Parameter Preliminary VT6102 @+ t dah @+ t trval trhold Width (ns) Max.( 8.2, 12.1, 21.3) 2 Min( 5.8, 8.5, 15.0) Max( 8.4, 12.1, 21.9) 2 Min( 5.8, 8.5, 15. ...
Page 39
... TRDY# hold time Note : 1.(xxx, xxx, xxx) : (best, normal, worst) 2.Cfg read only Ver_01 ccccccccccccc hfrhhhhhhhhhh znondddddozzz znxddddddozzz hhfllllllkhhh hhhhhhhhfrhhh \\@+ t daval Parameter Preliminary VT6102 @+ t dah @+ t trval trhold Width (ns) ( 8.2, 12.1, 21.3) ( 5.8, 8.5, 15.0) ( 4.6, 6.7, 11.8) ( 3.1, 4.6, 8.2) 39 Note ...
Page 40
... All of MDIO signals transition occure in negative egde of MDC. Ver_01 ccccc//cccccc lrhhh//hhhhhf znxxx//xxxxxo @+ ttxeval, ttxdval0 @+ t txdval1 Parameter Preliminary VT6102 @+ ttxeh, ttxdh, Width (ns) Note ( 3.7, 5.4, 9.5) ( 3.6, 5.3, 9.3) Min.( 3.5, 5.1, 8.9) Max.( 5.8, 8.6, 15.1) ( 5.9, 8.7, 15. ...
Page 41
... BPRD# is deasserted to the PCLK rising edge which latches TRDY# Note : 1.Delay transaction control bit : PCI cfg/7ah/bit5 2.(xxx, xxx, xxx) : (best, normal, worst) 3.DTSEL : PCI cfg/7ah/bit4 Ver_01 + Parameter Preliminary VT6102 PCICLK +z t @’ bt max (ns) min (ns) (485, 487, 492) (29.5, 29.4, 28.9) (509, 508, 508) (299,298,298) (DTSEL=1) (DTSEL=0) (29 ...
Page 42
... STOP# hhhhfrhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh ;zzzzzzzzzzzz \\\@+ sval Symbol tff The initial FRAME# to the second valid FRAME# tsval PCICLK rising edge to STOP# Valid Delay tsh STOP# hold time Ver_01 Parameter Preliminary VT6102 zzzzzzzzz@’ (ns) min (3300, 3300, 3300) ( 5.4, 8.0, 14.1) ( 3.8, 5.6, 9.8) Note 42 ...
Page 43
... MD[7:0] zzzzzzzzzznddddozzzzzz +z?T Symbol Parameter T AS Address Setup Time T AA Address Cycle Time T RP BPRD# Pulse Width T RD Read Access Time T DH Data Hold Time Ver_01 T zz @+? Timing 116 423 270 298 61 zzzzz +? Timing 85 508 330 230(max) 0 (max) Preliminary VT6102 Unit Unit ...
Page 44
...
Page 45
... VIA Technologies, Inc PPLICATION SCHEMATIC Ver_01 Preliminary VT6102 45 ...
Page 46
... VIA Technologies, Inc. Ver_01 Preliminary VT6102 46 ...
Page 47
... VIA Technologies, Inc. 8. Package Mechanical Specifications Ver_01 Preliminary VT6102 47 ...