MT8986AP Zarlink Semiconductor, MT8986AP Datasheet

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MT8986AP

Manufacturer Part Number
MT8986AP
Description
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Applications
* 44 Pin only
* STi10
* STi11
* STi12
* STi13
* STi14
* STi15
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
256 x 256 or 512 x 256 switching configurations
8-bit or 4-bit channel switching capability
Guarantees frame integrity for wideband
channels
Automatic identification of ST-BUS/GCI
interfaces
Accepts serial streams with data rates up to
8.192 Mb/s
Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
Programmable frame offset on inputs
Per-channel three-state control
Per-channel message mode
Control interface compatible to Intel/Motorola
CPUs
Low power consumption
Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
MVIP
Serial bus control and monitoring
Centralized voice processing systems
Voice/Data multiplexer
32 kbit/s channel switching
interface functions
Converter
Parallel
Serial
to
CLK FR AS/
Timing
Unit
ALE
Figure 1 - Functional Block Diagram
Multiple Buffer Data
IM
*
DS
RD
Memory
Microprocessor
CS
Interface
Internal Registers
R/W
WR
A0/
A7
V
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital
Switch (DX). It is pin compatible with the MT8980D
and retains all of its functionality. This device is
designed to provide simultaneous connections (non-
blocking) for up to 256 64kb/s channels or blocking
connections for up to 512 64kb/s channels. The
serial inputs and outputs connected to MT8986 may
have 32 to 128 64kb/s channels per frame with data
rates ranging from 2048 up to 8192 kb/s. The
MT8986 provides per-channel selection between
variable and constant throughput delays allowing
voice and grouped data channels to be switched
without corrupting the data sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The
MT8986 is ideal for medium size mixed voice and
data switching/processing applications.
CMOS ST-BUS  FAMILY
Description
DD
DTA AD7/
V
SS
AD0
MT8986AE
MT8986AP
MT8986AL
Multiple Rate Digital Switch
Connection
Output
Memory
CSTo
MUX
Ordering Information
-40 ° C to +85 ° C
40 Pin Plastic DIP
44 Pin PLCC
44 Pin QFP
ISSUE 4
Converter
Parallel
Serial
ODE
to
MT8986
March 1997
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
2-63

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MT8986AP Summary of contents

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... STi14 * STi15 CLK FR AS Pin only ALE CMOS ST-BUS  FAMILY MT8986AE MT8986AP MT8986AL Description The Multiple Rate Digital Switch (MRDX upgraded version of Zarlink's MT8980D Digital Switch (DX pin compatible with the MT8980D and retains all of its functionality. This device is designed to provide simultaneous connections (non- blocking) for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels ...

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MT8986 STi3 8 STi4 9 STi5 10 STi6/A6 11 STi7/A7 12 VDD CLK 15 STi8/A0 16 STi9/A1 STi10/ ...

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Pin Description (continued) Pin # Name DIP PLCC QFP STi6/A6 ST-BUS Input 6/Addr.6 input (Input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus is used along ...

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MT8986 Pin Description (continued) Pin # Name DIP PLCC QFP STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin is determined by the switching configuration enabled. If non-multiplexed CPU bus ...

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DEVICE OVERVIEW With the integration of voice, video and data services in the same network, there has been an increasing demand for systems which ensure that data kbit/s rates maintain sequence integrity while being transported through ...

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MT8986 be output. The Connect Memory Low data is transmitted on to the output every frame until it is changed by the CPU with a new data. The features of each output channel in the MT8986 are controlled by the ...

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IMS register). In case of different I/O rates (DMO bit HIGH), the switching configuration is always non-blocking with different number of I/O streams which is defined by the IDR and ODR bits (see IMS register). ...

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MT8986 Interface Number of Serial Clock Interface required at Data Rate CLK Pin (MHz) 2 Mb/s 4.096 2 Mb/s 4.096 * 2 Mb/s 4.096 * Nibble 4.096 Switching (2 Mb/s) 4 Mb/s 4.096 4 Mb/s 4.096 8 Mb/s 8.192 Table ...

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Register (FIO). If this function is not required in the user's applications, the FIO register should be set up during system initialization to a state where offset functions are disabled. Delay Through the MT8986 The switching of information from the ...

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MT8986 Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Table 4. Constant Throughput Delay values operations by making use of a multiple Data-Memory buffer technique. The input channels written in any of the buffers during frame N will be read ...

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The Control and Interface Mode Selection registers together control all the major functions of the device. The Interface Mode Select register should be set up during system power-up to establish the desired switching configuration as explained in the Serial Interface ...

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MT8986 CMH is transmitted during ST-BUS channel 31 bit 6. For more detailed description of the CSTo operation, see section 6 of Application Note MSAN-123. The Bit V/C (Variable/Constant Delay) of each Connect Memory High location allows the per- channel ...

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SM BIT NAME 7 SM Split Memory. When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits ...

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MT8986 Identical # of Input x select subsections I/O Output Rate Streams 2 Mb/s 8x8 STA2, STA1, STA0 2 Mb/s * 4x4 * STA1, STA0 2 Mb/s * 16x8 * STA3, STA2, STA1, STA0 4 Mb/s 4x4 STA1, STA0 4 ...

Page 15

Interface Mode Selection Register - Read/Write 7 6 DMO IDR1 BIT NAME 7 DMO Device Main Operation. This bit is used by the CPU to define one of the two main operations of the MT8986 device. If this bit is ...

Page 16

MT8986 Data Rate Selected DMO Bit at IDR bits (Mb/s) 2.048 LOW Identical I/O Rates 4.096 8.192 HIGH Input/Output Rate selected in Different I/O IDR/ODR bits Rates Table 8. Switching Configurations for Identical I/O Rates ** 44 pin packages only ...

Page 17

Connection Memory High - Read/Write 7 X BIT NAME 6 V/C Variable/Constant Throughput Delay Mode. This bit is used to select between Variable (LOW) and Constant Delay (HIGH) modes in a per-channel basis. Tables 1 and 2 describe the switching ...

Page 18

MT8986 Connection Memory Low - Read/Write 7 SAB2 BIT NAME 7-5 SAB2-0* Source Stream Address bits. These three bits are used together with SAB3 in CMH to select different source streams for the connection. Depending on the ...

Page 19

Stream Pair Selection Register - Read/Write (ONLY PROVIDED IN THE 44 PIN PACKAGES BIT NAME 5-3 SPA2-0 Stream Pair A selection. These three bits define which pair of streams are going to be connected to the switch matrix, ...

Page 20

MT8986 Applications Switch Matrix Architectures The MT8986 is an ideal device for designs of medium size switch matrix. For applications where voice and grouped data channels are transported within the same frame, the voice samples have to be time interchanged ...

Page 21

MT8986 device allows cost effective implementations of Non-Blocking matrices ranging up to 1024 channels. Figures 12 and 13 show the block diagram of implementations with Non-Blocking capacities of 512 and 1024-channel, respectively. Interfacing MT8986 ...

Page 22

MT8986 8 MT8986 Address 8 Decode RES RST 8051 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE RD WR Figure 14 - Interfacing the MT8986 to the 8051 Microcontroller during a read cycle whenever DTA goes low. When writing ...

Page 23

Absolute Maximum Ratings* Parameter Voltage on Digital Inputs 3 Voltage on Digital Outputs 4 Current at Digital Outputs 5 Storage Temperature 6 Package Power Dissipation * Exceeding these values may cause permanent damage. ...

Page 24

MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 Frame Pulse width 2 Frame Pulse setup time 3 Frame Pulse hold time 4 STo delay Active to Active 5 STi setup time 6 ...

Page 25

AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 Clock Period 2 Pulse Width 3 Frame Width High 4 Frame Setup 5 Frame Hold 6 Data Delay/Clock Active to Active 7 Serial Input Setup ...

Page 26

MT8986 AC Electrical Characteristics Characteristics 1 O STo0/9 Delay - Active to High STo0/9 Delay - High Z to Active Output Driver Enable Delay CSTo Output Delay S † Timing is ...

Page 27

AC Electrical Characteristics - Serial Streams at 4.096 and 8.192 Mb/s (refer to Figures 20-25) Characteristics 6 Frame Sync Width 4.096Mb/s 8.192Mb/s 7 Valid Data Delay from CK Input 4.096Mb/s 8.192Mb/s 8 Input Data Setup 4.096Mb/s 8.192Mb/s 9 Input Data ...

Page 28

MT8986 CLK (4.096 or 8.192 MHz (positive Ch 127 STo Bit 7 Bit 5 STi CLK (4.096 MHz (negative Ch. 63 ...

Page 29

CLK (4.096 MHz (positive Ch. 63 Ch. 0 STo Bit 0 Bit Ch. 31 STi Bit 0 CLK (4.096 MHz (negative Ch. 31 STo Bit 0 Ch. ...

Page 30

MT8986 CLK (4.096 MHz (positive Ch. 63 STo Bit 0 Ch. 31 STi Bit 0 CLK (4.096 MHz (negative Ch. 63 STo Bit 0 Ch. 31 STi Bit ...

Page 31

CLK (8.192 MHz Ch. 127 Ch. 0 STi Bit 0 Bit Ch. 31 STo Bit 0 Figure 24 - Rate Conversion Mode (DMO bit= Mb Mb/s CLK (8.192 ...

Page 32

MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup ...

Page 33

ALW ALE t t ADS ADH AD0- ADDRESS AD7 t ALRD ALWR DTA Figure 26 - Intel/National Multiplexed Bus Timing DATA t SWD CSR CSW t DSW t DDR ...

Page 34

MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 ...

Page 35

DS R/W t ASW AS t ADS AD7-0 ADDRESS WR AD7-0 ADDRESS RD CS DTA Figure 27 - Motorola Multiplexed Bus Timing t RWS t DSH ADH SWD DATA t CSS t DDR t AKD MT8986 2.0V ...

Page 36

MT8986 AC Electrical Characteristics Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 CS Setup from DS rising 2 R/W Setup from DS rising 3 Add setup from DS rising 4 CS hold after DS falling 5 ...

Page 37

DS CS R/W A0-A6 D0-D7 READ D0-D7 WRITE DTA Figure 28 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID DATA t t DSW SWD VALID DATA t t DDR DHW t AKD MT8986 2.0V 0.8V t ...

Page 38

MT8986 Notes: 2-100 ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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