MT9079AP Zarlink Semiconductor, MT9079AP Datasheet
MT9079AP
Related parts for MT9079AP
MT9079AP Summary of contents
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... C4i/C2i F0i CMOS ST-BUS FAMILY MT9079AE MT9079AL MT9079AP Description The MT9079 is a feature rich E1 (PCM 30, 2.048 Mbps) link framer and controller that meets the latest CCITT and ETSI requirements. The MT9079 will interface to a 2.048 Mbps backplane and can be controlled directly by a parallel processor, serial controller or through the ST-BUS ...
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MT9079 1 40 RESET 2 39 DSTo RxDL 3 38 TxDL DLCLK IRQ D0\SIO\CSTo0 ...
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Pin Description Pin # Name DIP PLCC QFP RESET RESET (Input): Low - maintains the device in a reset condition. High - normal operation. The MT9079 should be reset after power-up. The time constant for a power-up ...
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MT9079 Pin Description (Continued) Pin # Name DIP PLCC QFP R/W Read/Write (Input): High - the parallel processor is reading data from the MT9079. [P] Low - the parallel processor is writing data to the MT9079. RxD ...
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Pin Description (Continued) Pin # Name DIP PLCC QFP RxMF Receive Multiframe Boundary (Output): An output pulse delimiting the received multiframe boundary. The next frame output on the data stream (DSTo) is basic frame zero on the ...
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MT9079 Functional Description The MT9079 is an advanced PCM 30 framer that meets or supports the layer Recommendations of G.703, G.704, G.706, G.775, G.796 and G.732 for PCM 30; I.431 for ISDN Primary Rate; and T1.102 for DS1A. It also ...
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Therefore, ST-BUS bit 7 is synonymous with PCM 30 bit 1; bit 6 with bit 2: and so on. See Figure 33. PCM 30 time slot zero is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication of ...
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MT9079 G.704 and G.732 for more details on CAS mutliframing requirements. A CAS signalling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition rate of 2 msec. It should be noted that the ...
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CAR data page number). Second, each page has a maximum of 16 registers that are addressed on a read or write to a non-CAR address (non-CAR: address AC4 = 1, AC3-AC0 = register address, ...
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MT9079 interface. See Tables 13, 14, 16 and 17 for CAS bit positions in CSTo1 and CSTi2. Reset Operation (Initialization) The MT9079 can be reset using the hardware RESET pin (see pin description for external reset circuit requirements) or the ...
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TAIS Operation The TAIS (Transmit AIS) pin allows the PRI interface to transmit an all ones signal form the point of power-up without writing to any control registers. After the interface has been initialized normal operation can take place by ...
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MT9079 Elastic Buffer When control bit RDLY=0, the MT9079 has a two frame receive elastic buffer, which absorbs wander and low frequency jitter in multi-trunk applications. The received PCM 30 data (RxA and RxB) is clocked into the elastic buffer ...
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RxTS4-0 and RxBC2- controlling the position of the F0i pulse with respect to the received time slot zero position. The phase status word bits RxTS4-0 and RxBC2-0 will also indicate the delay in ...
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MT9079 >914 CRC errors in one second No CRC multiframe alignment. 8 msec. timer expired* CRC-4 multi-frame alignment Start 400 msec timer. Note 7. Start 8 msec timer. Note 7. Find two CRC frame alignment signals. Note 7. CRC multiframe ...
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Therefore, the primary basic frame alignment will not be updated during the CRC-4 multiframing search, but will be updated when the CRC-4 multiframing search is complete. Channel Signalling When control bit TxCAS is low the MT9079 is in Channel ...
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MT9079 Bits 7 and 6 of page 1, address 15H (COD1-0) determine the PCM 30 format of the PCM 30 transmit and receive signals. The RZ format (COD1-0 = 00) can be used where the line interface is implemented with ...
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CRC-4 errors and E-bit errors are counted by the MT9079 in order to support compliance with CCITT requirements. These eight bit counters are located on page 4, addresses 1FH and 1EH respectively. They are incremented by single error events, which ...
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MT9079 The MT9079 is equipped with two 16 byte circular receive buffers and two 16 byte circular transmit buffers, which can be connected to any PCM 30 time slot. Connection is made through control bits the ...
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DWM7-0 - Detect Word Mask (page 1, address 19H eight bit code, which determines the bits that will be considered in the comparison between the receive data and the Code Detect Word (CDW7-0). If ...
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MT9079 four, which are located on page 1, addresses 1BH to 1EH. After a MT9079 reset (RESET pin or RST control bit) all interrupts of mask words one, two and three are masked; and the interrupts of mask word zero ...
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Address ( 10H (Table 40) Error and Debounce Selection Word 11H (Table 41) Bit Error Rate Compare Word 12H (Table 42) Circular Buffer Accumulate Control Word 13H - 14H Unused. ...
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MT9079 Address ( 10H - 11H Unused. 12H (Table 59) Interrupt Vector 13H - 17H Unused 18H (Table 60) Bit Error Rate Counter 19H (Table 61) RAI and Continuous CRC ...
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Per Channel Receive Signalling (Page 6) Page 06H, addresses 10001 to 11111 contain the Receive Signalling Control Words for PCM 30 channels and 16 to 30. Bit Name Functional Description A(n), Receive Signalling Bits ...
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MT9079 Bit Name Functional Description 3 TBUF0 Transmit Buffer Zero Connect. If one, the contents of the transmit circular buffer zero will be transmitted in the corresponding time slot beginning at the next multiframe boundary. If zero, circular buffer zero ...
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Transmit National Bit Buffer (Page D) Page 0DH, addresses 10000 to 10100 contain the five bytes of the transmit national bit buffer (TNBB0 - TNBB4 respectively). This feature is functional only in processor and controller modes when control bit NBTB=1. ...
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MT9079 Bit Name Functional Description 7 TIU0 Transmit International (0) When CRC-4 operation is disabled, this bit is transmitted on the PCM 30 2048 kbit/sec. link in bit position one of time-slot zero of frame-alignment frames reserved for ...
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Bit Name Functional Description TMA1-4 Transmit Multiframe Alignment Bits (0000) One to Four. These bits are transmit- ted on the PCM 30 2048 kbit/sec. link in bit positions one to four of time slot 16 of frame ...
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MT9079 Bit Name Functional Description 7 TAIS Transmit Alarm Indication Signal. If (0) one, an all ones signal is transmitted in all time slots except zero and 16. If zero, these time slots function nor- mally. 6 TAIS0 Transmit Alarm ...
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Bit Name Functional Description 7 RDLY Receive Delay. If one, the receive (0) elastic buffer will be one frame in length and controlled frame slips will not occur. The RSLIP and RSLPD status bit will indicate a buffer under- flow ...
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MT9079 Bit Name Functional Description 7 EBI Receive E-bit (0) unmasked an interrupt is initiated when a receive E-bit indicates a remote CRC-4 error unmasked masked. Interrupt 00100000. 6 CRCI CRC-4 Error (0) unmasked an interrupt ...
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Bit Name Functional Description 7 MFSYI Multiframe Synchronization rupt. When unmasked an interrupt is (0) initiated when multiframe synchroni- zation is lost unmasked masked. Interrupt 10000000. 6 CSYNI CRC-4 Multiframe Alignment. When unmasked an interrupt is ...
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MT9079 Bit Name Functional Description CMP7 Bit Error Rate Compare Word CMP7 is the most significant bit and CMP0 CMP0 is the least significant bit of a bit (00H) pattern that is compared ...
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Bit Name Functional Description BRLD7 Bit Error Rate Load Word. This bit - pattern is loaded into the bit error BRLD0 rate counter when LDBER is toggled (valid in ST-BUS mode only). Table 44 - Bit Error ...
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MT9079 Status Page 3 Tables describe the bit functions of the page 3 status registers. Bit Name Functional Description 7 SYNC Receive Basic Frame Alignment. Indicates the basic frame alignment status (1 - loss acquired). ...
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Bit Name Functional Description 7 RIU1 Receive International Use 1. This bit is received on the PCM 30 2048 kbit/sec. link in bit position one of the non-frame alignment signal used for CRC-4 multiframe alignment or international use. ...
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MT9079 Bit Name Functional Description RxTS1-0 Receive Time Slot. The two least sig- nificant bits of a five bit counter that indicates the number of time slots between the ST-BUS frame pulse and E8Ko ...
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Status Page 4 Tables describe the bit functions of the page 4 status registers and counters. The Internal Vector Status Word is cleared automatically after it is read by the microprocessor. The RESET and RST functions do ...
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MT9079 Applications Microprocessor Interfaces Figure 7 illustrates a circuit which connects the MT9079 to a MC68HC11 microcontroller operating at 2.1 MHz. Address lines latched with the AS signal to generate one of eight possible Chip ...
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The data link transmit and receive signals are connected directly to port one. The DCLK signal is connected to INT1 so the 80C52 will be interrupted when new data link data needs to be transported. Figure 9 illustrates a circuit ...
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MT9079 The MC1455 RESET and HALT circuit has be taken from the MC68302 User's Manual. The reset circuit for the MT9079 (RC) must have a time constant that is at least five times the rise time of the power supply. ...
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START TAIS input = low Power-on Reset - RESET input = RC > power supply rise time SPND bit = 1 Write 00H to all control registers of pages 7 & 8 Select mode of operation. Note ...
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MT9079 Voice/Data Bus System Timing MT8980D STon STin CSTo MT8980 µP Interface +5V DTA 909Ω C4i C4 Figure 14 - Common Channel Signalling Control (Time Slot 16) through the MC68302 location. The BPV counter is cleared by writing zero to ...
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Common Channel Signalling Interface Figure 14 shows how to interface DSTi and DSTo time slot 16 to the MC68302 for the control of Common Channel Signalling (CCS) data. As can be seen in the timing diagram, the MT8980D CSTo signal ...
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MT9079 MT9079 TxA DSTo TxB DSTi To Line C4i/C2i C4 Interface RxA RxB E2i TxMF RxMF To Data Link Controller Figure 15 - PCM-30 (E1) Trunk Cross-Connect using the MT9079 Transparent Mode Fibre Interface Figure 16 shows how the MT9079 ...
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Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage at Digital Inputs 3 Current at Digital Inputs 4 Voltage at Digital Outputs 5 Current at Digital Outputs 6 Storage Temperature 7 Package Power Dissipation * Exceeding these values may cause ...
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MT9079 AC Electrical Characteristics Characteristics 1 DS low 2 DS High 3 CS Setup 4 R/W Setup 5 Address Setup 6 CS Hold 7 R/W Hold 8 Address Hold 9 Data Delay Read 10 Data Active to High Z Delay ...
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AC Electrical Characteristics Characteristics 1 Clock Pulse Width High 2 Clock Pulse Width Low 3 CS Setup 4 CS Hold 5 Write Setup 6 Write Hold 7 Output Delay 8 Active to High Z Delay t CSS ...
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MT9079 AC Electrical Characteristics - Data Link Timing Characteristic 1 Data Link Clock Output Delay 2 Data Link Output Delay 3 Data Link Setup 4 Data Link Hold Notes: 1. The falling edge of DLCLK occurs on the channel 0, ...
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AC Electrical Characteristics - ST-BUS Timing Characteristic 1 C2i Clock Width High or Low 2 C4i Clock Width High or Low 3 Frame Pulse Setup 4 Frame Pulse Low 5 Serial Input Setup 6 Serial Input Hold 7 Serial Output ...
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MT9079 Frame 15 DSTo BIt Cells Bit 7 Bit 6 Bit 5 F0i C2i RxMF C4i RxMF Figure 23 - Receive Multiframe Functional Timing DSTi Bit 7 Bit 6 Bit 5 Bit Cells F0i C2i TxMF Figure 24 - Transmit ...
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C4i/C2i t MOD (1) RxMF t MS (1) TxMF (1) Note : These two signals do not have a defined phase relationship Figure 26 - Multiframe Timing Diagram (C4i/C2i = 4.096 MHz) AC Electrical Characteristics - E8Ko Timing Characteristic 1 ...
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MT9079 AC Electrical Characteristics - PCM 30 Transmit Timing Characteristic 1 Transmit Delay 2 Transmit Delay RZ Transmit PCM 30 Data C2i C4i TxA and TxB for RZ TxA and TxB for NRZ and NRZB AC Electrical Characteristics - PCM ...
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C2i C4i RZ TxA RZ TxB NRZB TxA NRZB TxB NRZ TxA NRZ TxB E2i RZ RxA RZ RxB NRZB RxA NRZB RxB NRZ RxA NRZ RxB Figure 30 - Transmit Functional Timing Figure 31 - Receive Functional Timing MT9079 ...
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MT9079 FRAME FRAME 15 0 TIME SLOT Most BIT Significant Bit (First) CHANNEL CHANNEL 0 31 Most Significant Bit (First) 4-260 2.0 ms • • • • • • • • FRAME TIME SLOT • • • • ...
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