GMS97C52 Hynix Semiconductor, GMS97C52 Datasheet

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GMS97C52

Manufacturer Part Number
GMS97C52
Description
Manufacturer
Hynix Semiconductor
Datasheet

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HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS

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GMS97C52 Summary of contents

Page 1

... HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS ...

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...

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Oct. 2000 Ver 3.1a Blank: 12MHz 16: 16MHz 24: 24MHz 40: 40MHz Blank: 40PDIP PL: 44PLCC Q: 44MQFP 1: 4k bytes 2: 8k bytes 4: 16k bytes 6: 24k bytes 8: 32k bytes C: 4.25~5.5V L: 2.7~3.6V Blank: 40PDIP PL: ...

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... GMS90C51 - 256 GMS90C52 - 256 GMS90C54 - 256 GMS90C56 - 256 GMS90C58 4K 128 GMS97C51 4K 128 GMS97C51H 8K 256 GMS97C52 8K 256 GMS97C52H 16K 256 GMS97C54 16K 256 GMS97C54H 24K 256 GMS97C56 24K 256 GMS97C56H 32K 256 GMS97C58 32K 256 GMS97C58H 128 GMS90L31 256 GMS90L32 - 128 ...

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Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • (EP)ROM • 128 8 RAM • 64K external program memory space • 64K external data ...

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Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • (EP)ROM • 256 8 RAM • 64K external program memory space • 64K external data ...

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Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • 16K/24K/32K bytes (EP)ROM • 256 8 RAM • 64K external program memory space • 64K external data ...

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INDEX CORNER P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 / P3.2 INT1 / P3 P3 P3.5 N.C.: Do not connect ...

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Oct. 2000 Ver 3. P1 T2EX / P1.1 P0.0 / AD0 2 39 P1.2 P0.1 / AD1 3 38 P1.3 P0.2 / AD2 4 37 P1.4 P0.3 / AD3 5 36 P1.5 P0.4 / ...

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P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 / P3.2 INT1 / P3 P3 P3.5 N.C.: Do not connect ...

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XTAL1 XTAL2 RESET EA/V ALE/PROG PSEN Oct. 2000 Ver 3. Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O 7 ...

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P1.0-P1.7 2-9 1 P3.0-P3.7 11, 10-17 13- XTAL2 40-44, I/O 1-3 Port ...

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XTAL1 21 19 P2.0-P2.7 24-31 21-28 PSEN 32 29 RESET 10 9 Oct. 2000 Ver 3. Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, ...

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ALE / 33 30 PROG P0.0-P0.7 36-43 32- N.C. 1,12 - 23, Output pulse for latching the low byte of the address during ...

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XTAL1 OSC & TIMING XTAL2 RESET EA/V PP ALE/PROG PSEN Interrupt Unit Serial Channel Oct. 2000 Ver 3.1a ROM/EPROM RAM 4K/8K/16K 128/256 8 24K/32K CPU Timer 0 Port 0 Timer 1 Port 1 Timer 2 Port 2 Port 3 Port ...

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MSB Bit No. 7 Addr Reset value of PSW (for BCD operations) Bank 0 selected, data address 00 Bank 1 selected, data address 08 Bank 2 selected, data ...

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SP 82H DPL 83H DPH 84H reserved 85H reserved 86H reserved 87H PCON 1) 89H TMOD 8AH TL0 8BH TL1 8CH TH0 8DH TH1 3) 8EH 3) 8FH reserved 1) Bit-addressable Special Function Register means that the ...

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A1H reserved A2H reserved A3H reserved A4H reserved A5H reserved A6H reserved A7H reserved 1) A9H reserved AAH reserved ABH reserved ACH reserved ADH reserved AEH reserved AFH reserved 1) B1H reserved B2H reserved B3H reserved B4H reserved B5H reserved ...

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F1H reserved F2H reserved F3H reserved F4H reserved F5H reserved F6H reserved F7H reserved 1) Bit-addressable Special Function Register means that the value is indeterminate and the location is reserved. 3) Address C9 is configured as below. ...

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CPU ACC B DPH DPL PSW SP Interrupt System IE IP Ports Serial Channels 3) PCON SBUF SCON Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 2 T2CON T2MOD RC2H RC2L TH2 TL2 ...

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P0 81H SP 82H DPL 83H DPH 87H PCON 88H TCON 89H TMOD 8AH TL0 8BH TL1 8CH TH0 8DH TH1 8EH † AUXR0 90H P1 98H SCON 99H SBUF A0H P2 A8H IE B0H P3 B8H IP † ...

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C8H T2CON C9H T2MOD CAH RC2L CBH RC2H CCH TL2 CDH TH2 D0H PSW E0H ACC F0H B † indicates resident in the GMS9XX54/56/58, not in 9XX51/52. 8EH C9H - : this bit location is reserved 18 (cont’d) Bit 7 ...

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Timer/counter 0 used as one 8-bit timer/counter and 3 one 8-bit timer Timer 1 stops f OSC P3.4/T0 P3.5/T1 Max. /24 OSC P3.2 / ...

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Auto Reload 16-bit 0 1 Capture 0 1 Baud Rate 1 X Generator 1 X Off X X Note: = falling edge reload upon over- flow ...

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Oscillator Timer 1 (16-bit timer) (8-bit timer with 8-bit auto reload) Timer 2 Oct. 2000 Ver 3.1a Serial data enters and exits through RxD. TxD outputs the shift ...

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Timer 0 Overflow Timer 1 Overflow Timer 2 Overflow P1.1/ T2EX EXEN2 T2CON.3 UART P3.2/ INT0 IT0 TCON.0 P3.3/ INT1 IT1 TCON.2 : Low level triggered : Falling edge triggered 22 TF0 TCON.5 ET0 IE.1 TF1 TCON.7 ET1 IE.3 TF2 ...

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RESET IE0 TF0 IE1 TF1 RI TI TF2 EXF2 External Interrupt 0 IE0 Timer 0 Interrupt TF0 External Interrupt 1 IE1 Timer 1 Interrupt TF1 Serial Channel Timer 2 Interrupt TF2 + EXF2 Oct. 2000 Ver 3.1a ...

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Idle mode ORL PCON, #01H Power-Down mode ORL PCON, #02H 24 - Enabled interrupt CPU is gated off - Hardware Reset CPU status registers maintain their data. Peripherals are active Hardware Reset Oscillator is stopped, contents of on- chip RAM ...

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Oct. 2000 Ver 3.1a 25 ...

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Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports Output ...

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Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make ...

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Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports Output ...

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Input low voltage Input high voltage Output low voltage (ports Output low voltage (port 0, ALE, PSEN) Output high voltage (ports Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 ...

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Input low voltage Input high voltage Output low voltage (ports Output low voltage (port 0, ALE, PSEN) Output high voltage (ports Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 ...

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A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal for port 0. ALE and ...

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Address to valid instruction in Address float to PSEN † Interfacing the GMS90 series to devices with float times permissible. This limited bus contention will not cause any damage to port 0 Drivers ...

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RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...

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ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid ...

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RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...

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ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid ...

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RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...

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ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid ...

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RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...

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ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid ...

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RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE Address valid ...

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ALE PSEN PORT 0 PORT LHLL t LLPL t t AVLL PLPH t LLIV t PLIV t AZPL t LLAX INSTR. A0- AVIV A8-A15 t PXAV t PXIZ t PXIX A0-A7 A8-A15 Oct. 2000 Ver ...

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ALE t LHLL PSEN RD t AVLL PORT 0 PORT 2 ALE t LHLL PSEN WR t AVLL A0-A7 from PORT DPL PORT 2 Oct. 2000 Ver 3.1a t LLDV t t LLWL RLRH t RLDV t ...

Page 48

V 0.5V CC 0.45V AC Inputs during testing are driven at V Timing measurements are made LOAD V LOAD V LOAD For timing purposes a port pin is no longer floating when a 100mV change from load ...

Page 49

CRYSTAL OSCILLATOR MODE 30pF 10pF for Crystals For Ceramic Resonators, contact resonator manufacturer. Oct. 2000 Ver 3.1a DRIVING FROM EXTERNAL SOURCE N.C. XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 External Oscillator Signal XTAL1 P-LCC-44/Pin 21 ...

Page 50

Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency P1.0-P1.7 P2.0-P2.4 PORT 0 P2.7 ENABLE Address: P1.0-P1.7 = A0-A7 P2.0-P2.5 = A8-A13 P3.4 = A14 Data: P0.0-P0.7 = D0- AVQV t - ...

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GMS97X51 GMS97X52 GMS97X54 GMS97X56 GMS97X58 Oct. 2000 Ver 3.1a E0 Manufacturer Device Manufacturer ID ...

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NOTE: GMS97X51/52: GMS97X54/56/58 A0-A7 PROGRAM DATA P0 P2.0 A8-A13 -P2.5 EA/V PP P3.4 A14 1 RST ALE/PROG 1 P3.6 1 P3.7 PSEN XTAL2 P2.7 P2.6 XTAL1 V SS 100 s 25 pulses to GND 100 ...

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RST Read Signature Program Code Data Verify Code Data Program encryption table Program security bit 1 Program security bit 2 1. “0” = Valid low for that pin, "1" = valid high for that pin 12.75V 0.25V ...

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In the GMS97X51/52 ALE/PROG Enlarged View In the GMS97X54/56/58 ALE/PROG 4~6MHz 50 25 PULSES Min 100 s 10 100 PULSES A0-A7 P2.0 P0 A8-A13 -P2.5 A14 P3.4 EA RST 1 ...

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Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG Data hold after PROG P2.7 (ENABLE) high setup to PROG PP V hold after PROG ...

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BSC 0.0075 UNIT: INCH min. 0.020 0.120 0.090 0.180 0.165 Oct. 2000 Ver 3.1a ...

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Oct. 2000 Ver 3.1a 2.075 2.045 0.065 0.100 BSC 0.045 UNIT: INCH 0.600 BSC 0.550 0.530 0-15 53 ...

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SEE DETAIL "A" 0.80 BSC UNIT: MM 0-7 1.03 0.73 1.60 REF DETAIL "A" Oct. 2000 Ver 3.1a ...

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Company Name Application Order Date Tel: Fax: Name & Signature: YYW W KOREA Customer Sample YYYY Risk Order YYYY Verification D ate Quantity Date Approval Date: Package Hynix ...

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