MT8920BP Zarlink Semiconductor, MT8920BP Datasheet
MT8920BP
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MT8920BP Summary of contents
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... BUSY, DCS Registers IRQ, 24/32 Control Registers IACK, MS1 A5, STCH MMS ST-BUS Parallel Access Circuit MT8920BE MT8920BP MT8920BS Description The ST-BUS Parallel Access Circuit (STPA) provides a simple interface between Zarlink’s ST-BUS and parallel system environments. Tx0 Dual Port Ram Rx0 ...
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MT8920B 1 28 C4i 2 27 F0i 26 IACK, MS1 3 25 STi0 DS R/ ...
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Data Sheet Pin Description (continued) Pin # Name 13 A5 Address Bit A5 (Mode 1). This input is used to extend the address range of the STPA. A5 selects internal registers when high and Tx/Rx RAM’s when low. A5 Address ...
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MT8920B Functional Description The STPA (ST-BUS Parallel Access) device provides a simple interface between Zarlink’s ST-BUS and parallel system environments. synchronous, time division, multiplexed bussing scheme with data streams operating at 2048 kbit/s. The ST-BUS is the primary means of ...
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Data Sheet 24/32 Channel Operation The STPA may be configured to operate channel or 24 channel device. This feature, which is available in all three modes of operation, is particularly useful in applications involving data access to ...
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MT8920B 6 Data Sheet ...
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Data Sheet ADDRESS BITS • • • • • • • • • • • • • • • ...
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MT8920B Timing information for data transfers on this interface is shown in Figure 14. The Mode 1 interface is designed to operate directly with a 68000-type asynchronous bus but can easily accommodate most other popular microprocessors as well. Control Registers ...
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Data Sheet Control Register 2 Bits µP Rx0 a) Control Register 2 Bits Tx0 µP Rx0 b) Control Register 2 Bits ...
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MT8920B Interrupt Modes and Servicing Static Interrupt Mode A static interrupt is caused when an incoming byte matches a predefined byte. The incoming byte from a selected channel is stored in Interrupt Image Register (1/2) where it is compared with ...
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Data Sheet Mode 2 - Fast RAM Mode Mode 2 operates as a high speed dual port RAM interface to the ST-BUS. Only the two transmit RAM’s, Tx0 and Tx1, and the receive RAM, Rx0 are active in this mode ...
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MT8920B connected directly enable the device appropriately. Common Bus MMS MS1 24/ MMS MS1 24/ Figure 9 ...
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Data Sheet MT8920B 13 ...
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MT8920B Digital Signal Processor to ST-BUS Interface Mode 2 allows many high speed devices to be easily connected to the ST-BUS. Figure 12 shows a TMS32020 digital signal processor interfaced to the ST-BUS through the STPA. This simple interface allows ...
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Data Sheet Connecting the STPA to a shared ST-BUS Line The STPA’s STo0 and STo1 outputs cannot be directly forced into a high impedance However, with some external logic, the STo0 output can be buffered by a three-state device, controlled ...
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MT8920B Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions ...
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Data Sheet AC Electrical Characteristics ± ° (V =5.0V 5%,T =- Characteristics †† 1 Address to DS (CS) Low †† (CS) Low 3 DS (CS) Low to DTACK Low 4 Valid ...
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MT8920B AC Electrical Characteristics ± ° (V =5.0V 5%,T =- Characteristics 1 OE Low to Valid Data 2 Address Access Time 3 CS Low to Valid Data 4 Output Disable 5 Address Setup Time 6 ...
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Data Sheet CHANNEL N - BIT 0 C4i READ ADDRESS N or WRITE ADDRESS ( CONDITION 1: Access begins before contention window and finishes before ST-BUS access - No contention. OE, R/W BUSY CONDITION ...
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MT8920B AC Electrical Characteristics ± ° ((V =5.0V 5%,TA=- Characteristics OE, WE, Address Enabled 2 C4i Low to Address Change OE, WE, Address Disabled 4 C4i Low to Output Enable ...
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Data Sheet CHANNEL N-1 BIT 0 BIT 7 C4i STCH t STC BIT 4 BIT 3 C4i STCH DCS t STC CHANNEL N BIT 6 BIT 5 t SCPW Figure 18 - Mode 3 STCH Timing Diagram CHANNEL N BIT ...
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MT8920B AC Electrical Characteristics ± ° 5. Characteristics 1 Clock C4i Period 2 Clock C4i Period High 3 Clock C4i Period Low 4 C4i Rise Time 5 C4i Fall ...
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Data Sheet CHANNEL CHANNEL 31 0 Bit BIT 7 Data Bus Figure 21 - Format of 2048 kbit/s ST-BUS Streams 2.0 V INPUTS 0.8 V 2.0 V OUTPUTS 0 6.0k LOAD A 125 µs ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...