LXT972ALC Intel Corporation, LXT972ALC Datasheet

no-image

LXT972ALC

Manufacturer Part Number
LXT972ALC
Description
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LXT972ALC
Manufacturer:
INTEL
Quantity:
29
Part Number:
LXT972ALC
Manufacturer:
ALTERA
Quantity:
996
Part Number:
LXT972ALC
Manufacturer:
ALTERA
0
Part Number:
LXT972ALC
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
LXT972ALC A4
Manufacturer:
INTEL
Quantity:
344
Part Number:
LXT972ALC A4
Manufacturer:
INTEL
Quantity:
2
Part Number:
LXT972ALC A4
Manufacturer:
INTEL/英特尔
Quantity:
20 000
Part Number:
LXT972ALC-A4
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
LXT972ALC.A4
Manufacturer:
INTEL
Quantity:
20 000
Part Number:
LXT972ALCA4
Manufacturer:
INTEL
Quantity:
20 000
Intel
3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
The LXT972A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs).
This document also supports the LXT972.
The LXT972A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT972A is fabricated with an advanced CMOS process and requires only a single 3.3 V
power supply.
Applications
Product Features
.
Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs)
3.3 V Operation.
Low power consumption (300 mW
typical).
10BASE-T and 100BASE-TX using a
single RJ-45 connection.
Supports auto-negotiation and parallel
detection.
MII interface with extended register
capability.
Robust baseline wander correction
performance.
Supports JTAG Boundary Scan
®
LXT972A
10/100 PCMCIA Cards
Cable Modems and Set-Top Boxes
Standard CSMA/CD or full-duplex
operation.
Configurable via MDIO serial port or
hardware control pins.
Integrated, programmable LED drivers.
64-pin Low-profile Quad Flat Package
(LQFP).
— LXT972ALC - Commercial (0
ambient).
Order Number: 249186-003
Datasheet
°
to 70
August 2002
°
C

Related parts for LXT972ALC

LXT972ALC Summary of contents

Page 1

... PCMCIA Cards Cable Modems and Set-Top Boxes Standard CSMA/CD or full-duplex operation. Configurable via MDIO serial port or hardware control pins. Integrated, programmable LED drivers. 64-pin Low-profile Quad Flat Package (LQFP). ° — LXT972ALC - Commercial ( ambient). Order Number: 249186-003 August 2002 ° C ...

Page 2

... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners. 2 ...

Page 3

Contents 1.0 Pin Assignments .............................................................................................................................10 2.0 Signal Descriptions ........................................................................................................................13 3.0 Functional Description ..................................................................................................................17 3.1 Introduction .......................................................................................................................17 3.1.1 Comprehensive Functionality .............................................................................17 3.1.2 OSP™ Architecture ............................................................................................17 3.2 Network Media / Protocol Support....................................................................................18 3.2.1 10/100 Network Interface ...................................................................................18 3.2.1.1 Twisted-Pair Interface ..........................................................................18 3.2.1.2 ...

Page 4

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.7 100 Mbps Operation ......................................................................................................... 30 3.7.1 100BASE-X Network Operations...................................................................... 30 3.7.2 Collision Indication ............................................................................................ 32 3.7.3 100BASE-X Protocol Sublayer Operations ....................................................... 32 3.7.3.1 PCS Sublayer ....................................................................................... 33 3.7.3.2 PMA Sublayer...................................................................................... 35 3.7.3.3 ...

Page 5

Figures 1 LXT972A Block Diagram...................................................................................................9 2 LXT972A 64-Pin LQFP Assignments ..............................................................................10 3 Management Interface Read Frame Structure ..................................................................20 4 Management Interface Write Frame Structure .................................................................20 5 Interrupt Logic ..................................................................................................................21 6 Initialization Sequence .....................................................................................................23 7 Hardware Configuration Settings .....................................................................................24 8 Link ...

Page 6

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 8 LXT972A Pin Types and Modes...................................................................................... 16 9 Hardware Configuration Settings ..................................................................................... 25 10 Carrier Sense, Loopback, and Collision Conditions......................................................... 29 11 4B/5B Coding ................................................................................................................... 34 12 BSR Mode of Operation ................................................................................................... 41 ...

Page 7

Revision History Page # 1 Added “JTAG Boundary Scan” to Product Features on front page. Modified 10 GND). 11 Modified Added note under 13 multi-function pins be tied to the inactive states and all outputs be left floating, if unused.” ...

Page 8

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 8 Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 ...

Page 9

Figure 1. LXT972A Block Diagram RESET Management / ADDR0 Mode Select MDIO MDC MDINT MDDIS TX_EN TXD<3:0> TX_ER TX_CLK LED/CFG<3:1> Collision COL Detect RX_CLK RXD<3:0> RXDV Carrier Sense CRS Error Detect RX_ER Datasheet Document #: 249186 Revision #: 003 Rev. ...

Page 10

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 1.0 Pin Assignments Figure 2. LXT972A 64-Pin LQFP Assignments REFCLK/ MDDIS 3 4 RESET 5 TXSLEW0 TXSLEW1 6 7 GND VCCIO 8 9 N/C 10 N/C GND 11 12 ADDR0 ...

Page 11

Table 1. LQFP Numeric Pin List Pin Symbol 1 REFCLK/ MDDIS 4 RESET 5 TxSLEW0 6 TxSLEW1 7 GND 8 VCCIO 9 N/C 10 N/C 11 GND 12 ADDR0 13 GND 14 GND 15 GND 16 GND ...

Page 12

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 1. LQFP Numeric Pin List (Continued) Pin Symbol 37 LED/CFG2 38 LED/CFG1 39 PWRDWN 40 VCCIO 41 GND 42 MDIO 43 MDC 44 N/C 45 RXD3 46 RXD2 47 RXD1 48 RXD0 ...

Page 13

Signal Descriptions Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused. Table 2. LXT972A MII Signal Descriptions LQFP Symbol Pin# 60 TXD3 59 TXD2 58 TXD1 ...

Page 14

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 2. LXT972A MII Signal Descriptions (Continued) LQFP Symbol Pin# 43 MDC 42 MDIO 64 MDINT 1. Type Column Coding Input Output Analog Open Drain. ...

Page 15

Table 4. LXT972A Miscellaneous Signal Descriptions (Continued) LQFP Symbol Pin# 39 PWRDWN 1 REFCLK/ 10, N Type Column Coding Input Output Analog Open Drain Table 5. LXT972A ...

Page 16

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 8. LXT972A Pin Types and Modes Modes RXD 0-3 HWReset DL SFTPWRDN DL HWPWRDN High ISOLATE IPLD 1. A High Z (High impedance) or three state determines when the ...

Page 17

Functional Description 3.1 Introduction The LXT972A is a single-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and 100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT972A can directly drive either a 100BASE-TX line ...

Page 18

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.2 Network Media / Protocol Support The LXT972A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair. 3.2.1 10/100 Network Interface The network interface port consists of two differential signal pairs. Refer to assignments. ...

Page 19

When the LXT972A receives a Remote Fault indication from its partner during auto-negotiation it does the following: • Sets Register bit 5.13 in the Link Partner Base Page Ability Register, and • Sets the Remote Fault Register bit 1.4 in ...

Page 20

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver MDIO Addressing The protocol allows one controller to communicate between two LXT972A chips. Pin ADDR0 is set high or low to determine the chip address. MDIO Frame Structure The physical interface consists of ...

Page 21

Figure 5. Interrupt Logic Event X Mask Reg Event X Status Reg . . . Per Event Force Interrupt 1. Interrupt (Event) Status Register is cleared on read. 3.3 Operating Requirements 3.3.1 Power Requirements The LXT972A requires three power supply ...

Page 22

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.4 Initialization When the LXT972A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use ...

Page 23

Figure 6. Initialization Sequence MDIO Control MDIO Controlled Operation (MDIO Writes Enabled) Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 3.4.3 Reduced Power Modes The LXT972A offers two power-down modes. 3.4.3.1 Hardware Power Down ...

Page 24

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.4.3.2 Software Power Down Software power-down control is provided by bit 0.11 in the Control Register (refer to page 60). During soft power-down, the following conditions are true: • The network port is ...

Page 25

Table 9. Hardware Configuration Settings Desired Mode Speed Auto-Neg Duplex 1 (Mbps) Half Low 10 Full Low Disabled Half Low 100 Full Low Half High 100 Only Full High Enabled Half Only High 10/100 Full or High Half 1. Refer ...

Page 26

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: • After power-up, power-down, or reset, the power-down recovery time, as specified in on page 56, must be exhausted ...

Page 27

MII Clocks The LXT972A is the master clock source for data transmission and supplies both MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link conditions. When the link is operating at 100 Mbps, the ...

Page 28

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 9. 10BASE-T Clocking TX_CLK (Sourced by LXT972A) RX_CLK (Sourced by LXT972A) XI Figure 10. 100BASE-X Clocking TX_CLK (Sourced by LXT972A) RX_CLK (Sourced by LXT972A) XI Figure 11. Link Down Clock Transition RX_CLK ...

Page 29

Loopback The LXT972A provides two loopback functions, operational and test (see paths are shown in Figure 3.6.7.1 Operational Loopback Operational loopback is provided for 10 Mbps half-duplex links when bit 16 Data transmitted by the MAC (TXData) ...

Page 30

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 10. Carrier Sense, Loopback, and Collision Conditions (Continued) Speed Duplex Condition Full-Duplex Half-Duplex, 10 Mbps Register bit 16 Half-Duplex, Register bit 16 Test Loopback is enabled when ...

Page 31

Figure 14. 100BASE-TX Data Path Standard Data Flow Parallel D0 to Serial D1 D2 Serial to D3 Parallel Scrambler Bypass Data Flow S0 Parallel to S1 Serial S2 Serial S3 to Parallel S4 As shown in Figure 13 on ...

Page 32

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 16. 100BASE-TX Reception with Invalid Symbol RX_CLK RX_DV RXD<3:0> preamble SFD SFD DA RX_ER 3.7.2 Collision Indication Figure 17 shows normal transmission. Upon detection of a collision, the COL output is asserted ...

Page 33

PCS Sublayer The Physical Coding Sublayer (PCS) provides the MII interface, as well as the 4B/5B encoding/ decoding function. For 100BASE-TX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TX_EN is de-asserted. ...

Page 34

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 11. 4B/5B Coding 4B Code Code Type DATA IDLE undefined CONTROL undefined undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined 1. The /I/ (Idle) code group is sent continuously between ...

Page 35

Table 11. 4B/5B Coding (Continued) 4B Code Code Type undefined undefined undefined 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. 3. ...

Page 36

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.7.3.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and de-scrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10BASE-T), as well as receiving polarity correction ...

Page 37

In 10BASE-T mode, the polynomial scrambler/de-scrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT972A and sent across the MII to the MAC. 3.8.1 10BASE-T Preamble Handling The LXT972A offers two options for preamble handling, selected ...

Page 38

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.8.5 10T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT972A. To enable this function, set Register bit 16 When this function is ...

Page 39

LED Functions The LXT972A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately one second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to conditions: • ...

Page 40

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 20. LED Pulse Stretching Event LED stretch Note: The direct drive LED outputs in this diagram are shown as active Low. 3.10 Boundary Scan (JTAG1149.1) Functions LXT972A includes a IEEE 1149.1 boundary ...

Page 41

Table 12. BSR Mode of Operation Mode System Function Table 13. Supported JTAG Instructions Name EXTEST 1111 1111 1110 1000 IDCODE 1111 1111 1111 1110 SAMPLE 1111 1111 1111 1000 HIGHZ 1111 1111 1100 1111 CLAMP ...

Page 42

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 4.0 Application Information 4.1 Magnetics Information The LXT972A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated at 2kV to protect the circuitry from ...

Page 43

Figure 21. Typical Twisted-Pair Interface - Switch LXT972A 1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center-tap from a 2.5 V current source. A separate ferrite bead ...

Page 44

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 22. Typical Twisted-Pair Interface - NIC LXT972A 1. Center tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center tap from ...

Page 45

Test Specifications Note: Table 17 through Table 36 the LXT972A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in operating conditions specified in 5.1 Electrical Parameters Table 17. Absolute Maximum Ratings ...

Page 46

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 19. Digital I/O Characteristics Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage 1. Applies to all pins except MII, LED and XI/XO pins. Refer to ...

Page 47

Table 22. I/O Characteristics - LED/CFG Pins (Continued) Parameter Input Current Output Low Voltage Output High Voltage Table 23. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot/Undershoot ...

Page 48

... Table 26. LXT972A Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - JT 48 Sym Min Typ Max – 150 LR AX Tlt 8 – 24 Tlpw 60 – 150 LXT972ALC 1.4 64LQFP 58 C/W 27 C/W 3.4 C/W Units Test Conditions ms – ms – ns – Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 ...

Page 49

Timing Diagrams Figure 24. 100BASE-TX Receive Timing - 4B Mode RX_DV RXD<3:0> RX_CLK Table 27. 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted ...

Page 50

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 25. 100BASE-TX Transmit Timing - 4B Mode TXCLK TX_EN TXD<3:0> Table 28. 100BASE-TX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN ...

Page 51

Figure 26. 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPI COL Table 29. 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPIP RXD out (Rx latency) ...

Page 52

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 27. 10BASE-T Transmit Timing TX_CLK TXD, TX_EN, TX_ER CRS TPO Table 30. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN ...

Page 53

Figure 28. 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL Table 31. 10BASE-T Jabber and Unjabber Timing Parameters Parameter Maximum transmit time Unjab time 1. Typical values are at 25 °C and are for design aid only; not guaranteed and ...

Page 54

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 30. Auto Negotiation and Fast Link Pulse Timing TPO Figure 31. Fast Link Pulse Timing TPO Table 33. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse ...

Page 55

Figure 32. MDIO Input Timing MDC MDIO Figure 33. MDIO Output Timing MDC MDIO Table 34. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source ...

Page 56

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Figure 34. Power-Up Timing VCC MDIO,etc Table 35. Power-Up Timing Parameters Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed ...

Page 57

Register Definitions The LXT972A register set includes multiple 16-bit registers. Refer to register listing. • Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 ...

Page 58

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 58 Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 ...

Page 59

Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 59 ...

Page 60

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 39. Control Register (Address 0) Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6 Speed ...

Page 61

Table 40. MII Status Register #1 (Address 1) Bit Name 1.12 10 Mbps Full-Duplex 1.11 10 Mbps Half-Duplex 100BASE-T2 Full- Duplex 1.10 Not Supported 100BASE-T2 Half- Duplex 1.9 Not Supported 1.8 Extended Status 1.7 Reserved MF Preamble 1.6 Suppression Auto-Negotiation ...

Page 62

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 42. PHY Identification Register 2 (Address 3) Bit Name 3.15:10 PHY ID number Manufacturer’s 3.9:4 model number Manufacturer’s 3.3:0 revision number Read Only Figure 36. PHY Identifier Bit Mapping ...

Page 63

Table 43. Auto Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved Asymmetric 4.11 Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX 4.8 full-duplex 4.7 100BASE-TX 10BASE-T 4.6 full-duplex 4.5 10BASE-T Selector Field, 4.4:0 ...

Page 64

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 44. Auto Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved Asymmetric 5.11 Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX 5.8 ...

Page 65

Table 45. Auto Negotiation Expansion (Address 6) Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner 6.3 Next Page Able 6.2 Next Page Able 6.1 Page Received Link Partner A/N 6.0 Able Read ...

Page 66

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 47. Auto Negotiation Link Partner Next Page Receive Register (Address 8) Bit Name Next Page 8.15 (NP) Acknowledge 8.14 (ACK) Message Page 8.13 (MP) Acknowledge 2 8.12 (ACK2) Toggle 8.11 (T) Message/Unformatted ...

Page 67

Table 48. Configuration Register (Address 16, Hex 10) (Continued) Bit Name 16.2 Reserved Alternate NP 16.1 feature 16.0 Reserved 1. R/W = Read /Write, LHR = Latches High on Reset Table 49. Status Register #2 (Address 17) Bit Name 17.15 ...

Page 68

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 50. Interrupt Enable Register (Address 18) Bit Name 18.15:9 Reserved 18.8 Reserved 18.7 ANMSK 18.6 SPEEDMSK 18.5 DUPLEXMSK 18.4 LINKMSK 18.3 Reserved 18.2 Reserved 18.1 INTEN 18.0 TINT 1. R/W = Read ...

Page 69

Table 51. Interrupt Status Register (Address 19, Hex 13) (Continued) Bit Name 19.4 LINKCHG 19.3 Reserved 19.2 MDINT 19.1 Reserved 19.0 Reserved 1. R/W = Read/Write Self Clearing. Table 52. LED Configuration Register (Address 20, Hex 14) Bit ...

Page 70

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Table 52. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name LED2 20.11:8 Programming bits LED3 20.7:4 Programming bits 5 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write ...

Page 71

Table 53. Digital Config Register (Address 26) Bit 26.15:12 Reserved 26.11 MII Drive Strength 26.10 Reserved 26.9 Show Symbol Error 26.8:0 Reserved 1. R/W = Read /Write Read Only Latching High Table 54. Transmit Control Register ...

Page 72

... LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 7.0 Package Specification Figure 37. LXT972A LQFP Package Specifications 64-Pin Low Profile Quad Flat Pack • Part Number - LXT972ALC Commercial Temperature Range (0ºC to +70ºC) Dim Min A – 0.17 D 11. 11. θ θ ...

Page 73

... Product Ordering Information Table 55. Product Information Number DJLXT972ALC.A4 Figure 38. Ordering Information - Sample DJ LXT 972A Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver Revision Qualification E001 Build Format E000 E001 Qualification Q S Product Revision ...

Page 74

LXT972A 3.3 V Dual-Speed Fast Ethernet Transceiver 74 Datasheet Document #: 249186 Revision #: 003 Rev. Date: August 7, 2002 ...

Related keywords