GMS87C1202 Hynix Semiconductor, GMS87C1202 Datasheet
GMS87C1202
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GMS87C1202 Summary of contents
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Jan. 2002 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C1102 GMS81C1202 User’s Manual Ver 2.0 ...
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... ELECTRICAL CHARACTERISTICS - GMS87C1102, GMS87C1202 ......................... 19 11.1 Absolute Maximum Ratings - GMS87C1102, GMS87C1202 . . . . . . . . . . . . . . . . 19 11.2 Recommended Operating Conditions - GMS87C1102, GMS87C1202 . . . . . . . . . 19 11.3 DC Electrical Characteristics - GMS87C1102, GMS87C1202 . . . . . . . . . . . . . . . . 20 11.4 A/D Converter Characteristics - GMS87C1102, GMS87C1202 . . . . . . . . . . . . . . . 21 11.5 AC Characteristics - GMS87C1102, GMS87C1202 . . . . . . . . . . . . . . . . . . . . . . . 22 11.6 Typical Characteristics - GMS87C1102, GMS87C1202 . . . . . . . . . . . . . . . . . . . . 23 12. MEMORY ORGANIZATION ......................................................................................... 26 12.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 ...
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GMS81C1102 / GMS81C1202 13.2 RB and RBIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Device name ROM Size GMS81C1102 2K bytes GMS81C1202 2K bytes GMS87C1102 2K bytes(OTP) GMS87C1202 2K bytes(OTP) 1.2 Features • 2K bytes On-chip Program Memory • 128 Bytes of On-Chip Data RAM • Minimum Instruction execution time: - 500ns at 8MHz (2cycle NOP Instruction) • 2.2V to 6.0V Wide Operating Range • ...
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GMS81C1102 / GMS81C1202 2. BLOCK DIAGRAM(GMS81C1202) PSW RESET System controller System Clock Controller Timing generator Clock Xin Generator Xout Power Supply 3. PIN ASSIGNMENT(GMS81C1202) 20 DIP AN4 / RA4 1 AN5 / RA5 2 AN6 / ...
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BLOCK DIAGRAM(GMS81C1102) PSW RESET System controller System Clock Controller Timing generator Clock Xin Generator Xout Power Supply 5. PIN ASSIGNMENT(GMS81C1102) 16 DIP AN4 / RA4 1 AN5 / RA5 2 AN6 / RA6 3 AN7 ...
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GMS81C1102 / GMS81C1202 6. PACKAGE DIMENSION(GMS81C1202) 20 DIP MAX 4.57 0.46±0.07 20 SOP 2.5±0.15 0.42±0.08 4 26.2±0.3 MIN 0.38 3.3±0.25 TYP 2.54 1.45±0.2 7.5±0.1 12.8±0.2 0.2±0.1 TYP 1.27 unit : mm TYP 7.62 6.54±0 15° 0.25±0.05 10.35±0.2 0 ...
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PACKAGE DIMENSION(GMS81C1102) 16 DIP MAX 4.32 0.75±0.3 0.46±0.07 16 SOP 2.5±0.15 0.42±0.08 Jan. 2002 ver 2.0 19.2±0.2 MIN 0.38 3.3±0.25 TYP 2.54 1.45±0.2 7.5±0.1 10.25±0.05 0.18±0.05 TYP 1.27 0.27±0.04 GMS81C1102 / GMS81C1202 unit : mm TYP 7.62 6.3±0.3 0 ...
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GMS81C1102 / GMS81C1202 8. PIN FUNCTION V : Supply voltage Circuit ground RESET: Reset the MCU Input to the inverting oscillator amplifier and input to IN the internal clock operating circuit Output ...
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PORT STRUCTURES • RESET Internal RESET • Xin, Xout RC option fxin 4 STOP To System CLK • RA0/EC0 Data Bus Data Bus Data Bus Jan. 2002 ver 2 Data Reg. Direction Reg. ...
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GMS81C1102 / GMS81C1202 • RA1/AN1 ~ RA7/AN7 Data Bus Data Bus Data Bus To A/D Converter Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM • RB0 / AN0 / AVref Data Bus AVREFS Data Bus Data ...
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RB1/BUZ, RB4/PWM0/COMP PWM/COMP BUZ Data Bus Function Select Direction Reg. Data Bus Data Bus • RB2/INT0, RB3/INT1 Pull-up Select Data Bus Function Select Data Bus INT0 INT1 Data Bus • RC0, RC1 Data Bus Data Bus Data Bus Jan. ...
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GMS81C1102 / GMS81C1202 10. ELECTRICAL CHARACTERISTICS -GMS81C1102, GMS81C1202 10.1 Absolute Maximum Ratings - GMS81C1102, GMS81C1202 Supply voltage ........................................... -0.3 to +6.5 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (V ............................................................... -0.3 to ...
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DC Electrical Characteristics - GMS81C1102, GMS81C1202 • (V =4.5~6.0V, V =0V, f =1MHz~8MHz XIN Parameter Symbol V IH1 Input High Voltage V IH2 V IH3 V IL1 V Input Low Voltage IL2 V IL3 V Output ...
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GMS81C1102 / GMS81C1202 • (V =2.2~6.0V, V =0V, f =1MHz~4.2MHz XIN Parameter Symbol V IH1 V IH2 Input High Voltage V IH3 V IH4 V IL1 V IL2 Input Low Voltage V IL3 V IL4 V Output ...
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A/D Converter Characteristics - GMS81C1102, GMS81C1202 • (V =0V, V =3.072V/@f =4MHz XIN Parameter Analog Input Voltage Range Analog Power Supply Input Voltage Range Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale ...
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GMS81C1102 / GMS81C1202 10.5 AC Characteristics - GMS81C1102, GMS81C1202 (T =-20~+ =5V 10 Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time External Input Pulse Width RESET Input Width X IN RESET ...
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Typical Characteristics - GMS81C1102, GMS81C1202 This graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. In some graphs or tables the data presented are out- side specified operating range ...
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GMS81C1102 / GMS81C1202 = (mA 0.2 0 (mA) - ...
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IH1 f =4MHz X IN (V) Ta= IH3 f =4MHz ( Ta= ...
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GMS81C1102 / GMS81C1202 T ypical scillator F re quency ext=24pF Ta=25 C 2 0.5 0 2.5 3 3.5 T ypical R ...
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... Maximum current out of V pin ........................200 mA SS Maximum current into V pin ..........................150 mA DD Maximum current sunk by (I per I/O Pin) ........ Maximum output current sourced by (I ...............................................................................15 mA 11.2 Recommended Operating Conditions - GMS87C1102, GMS87C1202 Parameter Symbol V Supply Voltage DD Operating Frequency f XIN T Operating Temperature OPR Jan ...
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... RCOSC ( System CLK ) 1. RC0, RC1, RB1 and RB3 pins are applied for GMS87C1202 only. 2. Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 3. This parameter is valid when the bit PUPSELx is selected and set the Input mode or Interrupt Input Function. ...
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... A/D Converter Characteristics - GMS87C1102, GMS87C1202 (T = =0V, V =5.12V @ Parameter Analog Input Voltage Range Analog Power Supply Input Voltage Range Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time AV Input Current REF 1. This parameter is valid in the range from 02H to FFH, and typical value 1.3 LSB, maximum value 2.0 LSB in the other range (from 00H to 01H) ...
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... GMS81C1102 / GMS81C1202 11.5 AC Characteristics - GMS87C1102, GMS87C1202 (T =-20~+ =5V 10 Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width RESET Input Width X IN RESET INT0, INT1 EC0 22 =0V) SS Symbol Pins CPW RCP, FCP OUT ...
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... Typical Characteristics - GMS87C1102, GMS87C1202 This graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified V range). This is for imformation only and divices ...
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GMS81C1102 / GMS81C1202 = (mA IH1 X , RESET IN V IH1 f =4MHz XIN (V) Ta= ...
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T ypical scillator F re quency ext=24pF Ta=25 C 2 0.5 0 2.5 3 3.5 T ypical scillator ...
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GMS81C1102 / GMS81C1202 12. MEMORY ORGANIZATION The GMS81C1202 has separated address spaces for Pro- gram memory and Data Memory. Program memory can only be read, not written to. It can bytes of Pro- 12.1 Registers This ...
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C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. PSW NEGATIVE FLAG OVERFLOW FLAG BRK FLAG [Interrupt disable flag ...
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GMS81C1102 / GMS81C1202 12.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 2K bytes program memory space only the physically implemented. Accessing a loca- tion above FFFF will cause a ...
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PCALL in- stead of 3 bytes CALL instruction frequently called more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each ...
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GMS81C1102 / GMS81C1202 PCALL rel 4F35 PCALL 35H 0FF00H 0FF35H NEXT 0FFFFH Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED DW NOT_USED DW NOT_USED DW BIT_INT DW WDT_INT ...
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Data Memory Figure 12-6 shows the internal Data Memory space avail- able. Data Memory is divided into two groups, a user RAM(including Stack) and control registers DATA MEMORY (including STACK CONTROL REGISTERS FF ...
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GMS81C1102 / GMS81C1202 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When ...
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Address Name Bit 7 C0H RA RA Port Data Register C1H RAIO RA Port Direction Register C2H RB RB Port Data Register C3H RBIO RB Port Direction Register C4H RC RC Port Data Register C5H RCIO RC Port Direction Register ...
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GMS81C1102 / GMS81C1202 12.4 Addressing Mode The GMS87C1201 and GMS81C1202 use six addressing modes. • Register addressing • Immediate addressing • Direct page addressing • Absolute addressing • Indexed addressing • Register-indirect addressing Below example is shown for GMS81C1202. (1) ...
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0035 983500 INC !0035H data 0035 0FA00 0FA01 address: 0035 H 0FA02 00 H ...
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GMS81C1102 / GMS81C1202 Y indexed direct page (8 bit offset) This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y ...
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H 1725 ADC ...
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GMS81C1102 / GMS81C1202 13. I/O PORTS The GMS81C1202 has three ports, RA, RB and RC. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ...
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RB and RBIO registers 5-bit bidirectional I/O port (address C2 pin can be set individually as input and output through the RB Data Register ADDRESS : C2H RB RESET VALUE : Undefined RB4 RB3 R B ...
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GMS81C1102 / GMS81C1202 13.3 RC and RCIO registers 4-bit bidirectional I/O port (address C4 pin can be set individually as input and output through the RCIO register (address Data Register - - - ...
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CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and pe- ripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator ...
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GMS81C1102 / GMS81C1202 Vdd Rext Cext fxin 4 Figure 14-4 RC Oscillator Connections The oscillator frequency, divided output from the Xout pin, and can be used for test purpose or to synchroze other logic. To set the ...
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Basic Interval Timer The GMS81C1202 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 15-1 .The 8-bit Basic interval timer register (BITR) is in- creased every internal count pulse which ...
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GMS81C1102 / GMS81C1202 16. TIMER / COUNTER The GMS81C1202 has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two ...
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CAP0 CAP1 PWME Table 16-1 Operating ...
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GMS81C1102 / GMS81C1202 These timers have each 8-bit count register and data regis- ter. The count register is increased by every internal or ex- ternal clock input. The internal clock has a prescaler divide ratio option ...
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Timer/Counter Mode The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000 matches TDR0, TDR1 and then resets to 0000 match output generates Timer 0 interrupt not Timer ...
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GMS81C1102 / GMS81C1202 This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 16-8 , the pulse width of captured signal ...
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T0 Ext. INT0 Pin Interrupt Request ( INT0F ) Ext. INT0 Pin Interrupt Request ( INT0F ) Ext. INT0 Pin Interrupt Request ( INT0F ) Interrupt Request ( T0F ) T0 Figure 16-8 Excess Timer Overflow in Capture Mode Jan. ...
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GMS81C1102 / GMS81C1202 16.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external ...
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If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution T1CK[1:0] T1CK[1:0] = 00(125nS) = 01(250nS) 10-bit 7.8KHz 3.9KHz 9-bit 15.6KHz 7.8KHz 8-bit 31.2KHz 15.6KHz 7-bit 62.5KHz 31.2KHz Table 16-2 PWM Frequency vs. Resolution at ...
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GMS81C1102 / GMS81C1202 fxin PWM POL=1 PWM POL=0 Duty Cycle [ 80H x 125nS = 16uS ] Period Cycle [ 3FFH x 125nS = 127.875uS, 7.8KHz ] T1CK[1: fxin ) PWM0HR = ...
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Buzzer Output Function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable ...
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GMS81C1102 / GMS81C1202 18. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. ...
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A/D Control Register - - ADCM Reserved A/D Result Data Register ADCR ADCR7 ADCR6 ENABLE A/D CONVERTER A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT A/D START ( ADST = 1 ) NOP ADSF = 1 YES READ ADCR Figure 18-3 ...
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GMS81C1102 / GMS81C1202 (3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conver- sion is performed with any of pins AN0 to ...
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INTERRUPTS The GMS81C1202 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag("I" flag of PSW). The configuration of interrupt circuit is shown ...
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GMS81C1102 / GMS81C1202 Interrupt Enable Register High IENH INT0E INT1E Interrupt Enable Register Low IENL ADE WDTE Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled Disable 1 : Enable Interrupt Request Register ...
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System clock Instruction Fetch Address Bus Data Bus Internal Read Internal Write V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt ...
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GMS81C1102 / GMS81C1202 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK ...
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External Interrupt The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6 ) as shown in Figure 19 The edge detection of external interrupt has three transition ...
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GMS81C1102 / GMS81C1202 20. WATCHDOG TIMER The purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. The watchdog timer ...
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Power Saving Mode For applications where power consumption is a critical factor, device provides three kinds of power saving func- tions, STOP mode, Wake-up Timer mode and internal RC- oscillated watchdog timer mode. The power saving function is activated ...
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GMS81C1102 / GMS81C1202 level ( however, when the input level gets high than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at ...
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Oscillator (X pin) IN Internal Clock RESET Internal RESET Figure 21-3 Timing of STOP Mode Release by RESET 21.2 Wake-up Timer Mode In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler (only 2048 divided ratio) ...
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GMS81C1102 / GMS81C1202 21.3 Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The ...
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Oscillator (X pin) IN Internal RC Clock Internal Clock RESET RESET by WDT Internal RESET Figure 21-6 Internal RCWDT Mode Releasing by RESET. INPUT PIN internal V pull- GND X Weak pull-up current flows Figure 21-7 Application Example ...
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GMS81C1102 / GMS81C1202 22. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. ...
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POWER FAIL PROCESSOR The GMS81C1202 has an on-chip power fail detection cir- cuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/programmed) or disa- ble (if set) the Power-fail Detect circuitry low 3.0~4.0V ...
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GMS81C1102 / GMS81C1202 V DD Internal RESET V DD When PFDM = 1 Internal RESET V DD Internal RESET V DD System Clock When PFDM = System Clock 70 t < 64mS Figure 23-3 Power Fail Processor ...
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... The GMS87C1102/1202 is one-time PROM(OTP) microcontroller with 2K bytes electrically programmable read only mem- ory for the GMS81C1102/1202 system evaluation, first production and fast mass production. To programming the OTP device, user must use the universal programmer which is support Hynix Semiconductor. 24.1 Program Memory MAP Program Memory consists of configuration area and user program memory area. The configuration memory area has two parts (User ID & ...
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GMS81C1102 / GMS81C1202 User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RB0 (AVref/AN0) 7 RB2 (INT0) 8 RB4 (PWM/COMP OUT 11 ...
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V DD User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RB0 (AVref/AN0) 7 RB1 (BUZ) 8 RB2 (INT0) 9 RB3 (INT1) 10 RB4 (PWM/COMP ...
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GMS81C1102 / GMS81C1202 T SET1 EPROM Enable T V VPPS VPPR T VDDS 0V CTL0 0V CTL1 T CTL2 0V A_D7~ A_D0 V DD1H V DD High 8bit Address Input Figure 24-4 Timing Diagram in Program (Write ...
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Parameter Programming Supply Current Supply Current in EPROM Mode V Level during Programming PP V Level in Program Mode DD V Level in Read Mode DD CTL2~0 High Level in EPROM Mode CTL2~0 Low Level in EPROM Mode A_D7~A_D0 High ...
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GMS81C1102 / GMS81C1202 START Set DD1H Set Verify blank YES First Address Location Next address location N=1 EPROM Write 100uS program time Verify pass YES Apply 3N program cycle NO Last address YES 76 ...
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Next address location Jan. 2002 ver 2.0 START Set V =V DD2H DD Set V =V IHP PP First Address Location NO Last address YES Report Read =0V PP END Figure 24-7 Reading Flow Chart ...
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GMS81C1102 / GMS81C1202 78 Jan. 2002 ver 2.0 ...
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APPENDIX ...
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APPENDIX A. INSTRUCTION MAP 00000 00001 00010 00011 LOW HIGH SET1 BBS BBS 000 - dp.bit A.bit,rel dp.bit,rel 001 CLRC 010 CLRG 011 DI 100 CLRV 101 SETC 110 SETG 111 EI 10000 10001 10010 10011 ...
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GMS81C1102/GMS81C1202 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC 1 ADC #imm 2 ADC dp 3 ADC ADC !abs 5 ADC !abs + Y 6 ADC [ ADC [ dp ...
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NO. MNEMONIC 45 EOR #imm 46 EOR dp 47 EOR EOR !abs 49 EOR !abs + Y 50 EOR [ EOR [ EOR { X } ...
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GMS81C1102/GMS81C1202 2. REGISTER / MEMORY OPERATION NO. MNEMONIC 1 LDA #imm 2 LDA dp 3 LDA LDA !abs 5 LDA !abs + Y 6 LDA [ LDA [ ...
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OPERATION NO. MNEMONIC 1 ADDW dp 2 CMPW dp 3 DECW dp 4 INCW dp 5 LDYA dp 6 STYA dp 7 SUBW dp 4. BIT MANIPULATION NO. MNEMONIC 1 AND1 M.bit 2 AND1B M.bit 3 BIT dp ...
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GMS81C1102/GMS81C1202 5. BRANCH / JUMP OPERATION NO. MNEMONIC 1 BBC A.bit,rel 2 BBC dp.bit,rel 3 BBS A.bit,rel 4 BBS dp.bit,rel 5 BCC rel 6 BCS rel 7 BEQ rel 8 BMI rel 9 BNE rel 10 BPL rel 11 BRA ...
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CONTROL OPERATION & etc. NO. MNEMONIC 1 BRK NOP 5 POP A 6 POP X 7 POP Y 8 POP PSW 9 PUSH A 10 PUSH X 11 PUSH Y 12 PUSH PSW 13 ...