DS21Q44 Dallas Semiconductor, DS21Q44 Datasheet
DS21Q44
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DS21Q44 Summary of contents
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... IEEE 1149.1 support DESCRIPTION The DS21Q44 enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four framers that are configured and read through a common microprocessor compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer ...
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... INTRODUCTION The DS21Q44 is a superset version of the popular DS21Q43 Quad E1 framer offering the new features listed below. All of the original features of the DS21Q43 have been retained and software created for the original device is transferable to the DS21Q44. New Features Additional hardware signaling capability including: – ...
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... DS21Q44 ENHANCED QUAD E1 FRAMER Figure 1 105 DS21Q44 ...
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... INTRODUCTION .............................................................................................................................. 2 2. DS21Q44 PIN DESCRIPTION ......................................................................................................... 7 3. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................ 13 4. DS21Q44 REGISTER MAP............................................................................................................. 20 5. PARALLEL PORT........................................................................................................................... 24 6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 24 7. STATUS AND INFORMATION REGISTERS............................................................................. 34 8. ERROR COUNT REGISTERS....................................................................................................... 40 9. DS0 MONITORING FUNCTION................................................................................................... 43 10. SIGNALING OPERATION ............................................................................................................ 45 10.1 PROCESSOR BASED SIGNALING........................................................................................ 45 10.2 HARDWARE BASED SIGNALING........................................................................................ 48 11. PER– ...
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... INTERLEAVED PCM BUS OPERATION ................................................................................... 69 17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 72 17.1 DESCRIPTION.......................................................................................................................... 72 17.2 TAP CONTROLLER STATE MACHINE................................................................................ 73 17.3 INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................. 75 17.4 TEST REGISTERS.................................................................................................................... 77 18. TIMING DIAGRAMS...................................................................................................................... 82 19. OPERATING PARAMETERS ...................................................................................................... 92 20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 105 5 of 105 DS21Q44 ...
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... DOCUMENT REVISION HISTORY Revision Notes 12-22-98 Initial Release 6 of 105 DS21Q44 ...
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... DS21Q44 PIN DESCRIPTION Pin Description Sorted by Pin Number Table 2-1 PIN SYMBOL 1 TCHBLK0 2 TPOS0 3 TNEG0 4 RLINK0 5 RLCLK0 6 RCLK0 7 RNEG0 8 RPOS0 9 RSIG0 [RCHCLK0] 10 RCHBLK0 11 RSYSCLK0 12 RSYNC0 13 RSER0 14 VSS 15 VDD 16 SPARE1 [RMSYNC0] 17 RFSYNC0 18 JTRST* [RLOS/LOTC0] 19 TCLK0 20 TLCLK0 21 TSYNC0 22 TLINK0 A6/ALE (AS) 30 INT* 31 TSYSCLK1 ...
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... Receive Link Data from Framer 2 O Receive Link Clock from Framer 2 I Receive Clock for Framer 2 I Receive Bipolar Data for Framer 2 I Receive Bipolar Data for Framer 2 O Receive Signaling Output from Framer 2 [O] [Receive Channel Clock from Framer 2] - Signal Ground 8 of 105 DS21Q44 ...
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... Loss of Sync/Loss of Transmit clock from Framer 3] I Transmit Clock for Framer 3 O Transmit Link Clock from Framer 3 I/O Transmit Sync for Framer 3 I Transmit Link Data for Framer 3 I/O Data Bus Bit or Address/Data Bit 0; LSB I/O Data Bus Bit or Address/Data Bit 105 DS21Q44 ...
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... D6 or AD6 124 D7 or AD7 125 TSYSCLK0 126 TSER0 127 TSSYNC0 128 TSIG0 [TCHCLK0] Note: 1. Brackets [ ] indicate pin function when the DS21Q44 is configured for emulation of the DS21Q43, (FMS = 1). Pin Description Sorted by Pin Function, FMS = 0 Table 2-2 PIN SYMBOL 108 8MCLK ...
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... Receive Signaling Output from Framer 0 O Receive Signaling output from Framer 1 O Receive Signaling Output from Framer 2 O Receive Signaling Output from Framer 3 I/O Receive Sync for Framer 0 I/O Receive Sync for Framer 1 I/O Receive Sync for Framer 105 DESCRIPTION DS21Q44 ...
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... Transmit Signaling Input for Framer 3 I Transmit Sync for Elastic Store in Framer 0 I Transmit Sync for Elastic Store in Framer 1 I Transmit Sync for Elastic Store in Framer 2 I Transmit Sync for Elastic Store in Framer 3 I/O Transmit Sync for Framer 0 I/O Transmit Sync for Framer 105 DESCRIPTION DS21Q44 ...
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... VDD 111 VDD 14 VSS 78 VSS 110 VSS 63 WR*/(R/W*) 3. DS21Q44 PIN FUNCTION DESCRIPTION TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER ...
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... Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format (TCR1.7) control bit. Signal Name: TNEG Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter 105 DS21Q44 ...
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... Signal Type: Input /Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied 105 DS21Q44 ...
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... A 2.048 MHz reference clock used in the generation of 8MCLK. This function is available when FMS = 0. Signal Name: 8MCLK Signal Description: 8 MHz Clock Signal Type: Output A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is available when FMS = 105 DS21Q44 ...
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... FDL Status Register. Active low, open drain output. Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Set low to select DS21Q44 feature set. Set high to select DS21Q43 emulation. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select non– ...
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... IEEE 1149.1 Test Mode Select Signal Type: Input This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. If not used, this pin should be pulled high. This function is available when FMS = 105 DS21Q44 ...
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... Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. This function is available when FMS = 0. SUPPLY PINS Signal Name: VDD Signal Description: Positive Supply Signal Type: Supply 2.97 to 3.63 volts. Signal Name: VSS Signal Description: Signal Ground Signal Type: Supply 0.0 volts 105 DS21Q44 ...
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... DS21Q44 REGISTER MAP Register Map Sorted by Address Table 4-1 ADDRESS R BPV or Code Violation Count BPV or Code Violation Count CRC4 Error Count 1 / FAS Error Count CRC4 Error Count E-Bit Count 1 / FAS Error Count E-Bit Count 2 06 R/W Status 1 07 R/W Status 2 08 ...
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... Transmit Signaling 16 50 R/W Transmit Si Bits Align Frame 51 R/W Transmit Si Bits Non-Align Frame 52 R/W Transmit Remote Alarm Bits 53 R/W Transmit Sa4 Bits REGISTER NAME 21 of 105 DS21Q44 REGISTER ABBREVIATION TIR3 TIR4 TIDR RCBR1 RCBR2 RCBR3 RCBR4 RAF RS1 RS2 RS3 RS4 ...
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... R/W Transmit Channel 28 7C R/W Transmit Channel 29 7D R/W Transmit Channel 30 7E R/W Transmit Channel 31 7F R/W Transmit Channel 32 REGISTER NAME 22 of 105 DS21Q44 REGISTER ABBREVIATION TSa5 TSa6 TSa7 TSa8 RSiAF RSiNAF RRA RSa4 RSa5 RSa6 RSa7 RSa8 TC1 TC2 TC3 ...
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... Receive Channel Control 3 A7 R/W Receive Channel Control 4 A8 R/W Common Control Transmit DS0 Monitor AA R/W Common Control Receive DS0 Monitor REGISTER NAME 23 of 105 DS21Q44 REGISTER ABBREVIATION RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 ...
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... DS21Q44 is present. The T1 pin–for–pin compatible version of the DS21Q44 is the DS21Q42 and it also has an ID register at address 0Fh and the user can read the MSB to determine which chip is present since in the DS21Q42 the MSB will be set to a zero and in the DS21Q44 it will be set to a one ...
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... Power–Up Sequence The DS21Q44 does not automatically clear its register space on power–up. After the supplies are stable, each of the four framer’s register space should be configured for operation by writing to all of the internal registers. This includes setting the Test and all unused registers to 00Hex. ...
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... CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error 26 of 105 RESYNC CRITERIA 4.2 and 4.3.2 DS21Q44 ITU SPEC. G.706 4.1.1 4.1.2 G.706 G.732 5.2 ...
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... FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Transmit Timeslot 16 Data Select sample timeslot 16 at TSER pin 1 = source timeslot 16 from TS0 to TS15 registers 27 of 105 DS21Q44 (LSB) RBCS RESE (LSB) TSA1 TSM TSIO – ...
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... Sa5 bit. See Section 18 for timing details. Sa4 Bit Select. Set to one to source the Sa4 bit from the TLINK pin; set to zero to not source the Sa4 bit. See Section 18 for timing details 105 DS21Q44 (LSB) ODM AEBE PF ...
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... Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Receive G.802 Enable. See Section 18 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26 Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled 29 of 105 DS21Q44 (LSB) RG802 RCRC4 ...
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... See Section 10 or details. 0=do not force a freeze event 1=force a freeze event Receive Freeze Enable. See Section 10 for details. 0=no freezing of receive signaling data will occur 1=allow freezing of receive signaling data at RSIG (and RSER if CCR3.3=1 105 (LSB) LOTCMC RFF DS21Q44 RFE ...
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... AUTOMATIC ALARM GENERATION The DS21Q44 can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception, or loss of receive carrier (or signal) ...
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... If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details 105 DS21Q44 (LSB) TCM2 TCM1 TCM0 ...
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... Transmit Elastic Store Reset. Setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. Transmit data is lost during the reset. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set high 105 TCLKSRC RESR DS21Q44 (LSB) TESR ...
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... The specific details on the four registers pertaining to the HDLC controller are covered in Section 15 but they operate the same as the other status registers in the DS21Q44 and this operation is described below. When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one ...
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... Interrupt request pending. FRAMER 1 SR1 or SR2 INTERRUPT REQUEST interrupt request pending Interrupt request pending. FRAMER 0 HDLC CONTROLLER INTERRUPT REQUEST interrupt request pending Interrupt request pending. FRAMER 0 SR1 or SR2 INTERRUPT REQUEST interrupt request pending Interrupt request pending 105 DS21Q44 (LSB) F0HDLC F0SR ...
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... FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word 105 DS21Q44 (LSB) CRCRC FASRC CASRC 1 s). (LSB) ...
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... Receive Remote Alarm. Set when a remote alarm is received at RPOS and RNEG. Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1) consecutive zeros have been detected at RPOS and RNEG. Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream 105 DS21Q44 (LSB) RRA RCL RLOS ...
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... MF more than two zeros in two frames (512–bits) bit 3 of non–align frame set to zero for three consecutive occasions in 255–bit times, at least 32 ones are received LOTC RCMF DS21Q44 ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O ...
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... Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All Ones. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled 39 of 105 DS21Q44 (LSB) RRA RCL RLOS ...
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... Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Transmit Side Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled 40 of 105 DS21Q44 (LSB) LOTC RCMF TSLIP ...
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... MSB of the 16–bit code violation count LSB of the 10–bit code violation count (note 1) (note 1) (note 1) CRC4 CRC3 CRC2 NAME AND DESCRIPTION MSB of the 10–Bit CRC4 error count LSB of the 10–Bit CRC4 error count 41 of 105 DS21Q44 (LSB VCR1 V1 V0 VCR2 (LSB) CRC9 CRC8 CRCCR1 ...
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... LSB of the 10–Bit E–Bit Error Count FAS8 FAS7 FAS6 FAS2 FAS1 FAS0 NAME AND DESCRIPTION MSB of the 12–Bit FAS Error Count LSB of the 12–Bit FAS Error Count 42 of 105 DS21Q44 (LSB) EB9 EB8 EBCR1 EB1 EB0 EBCR2 (LSB) (note 2) (note 2) FASCR1 ...
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... DS0 MONITORING FUNCTION Each framer in the DS21Q44 has the ability to monitor one DS0 64Kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register ...
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... TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 13 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 9 for details 105 DS21Q44 (LSB (LSB) RCM2 ...
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... RDS0M.0 10. SIGNALING OPERATION Each framer in the DS21Q44 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and the hardware based signaling is covered in Section 10 ...
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... B(28) D(14) A(29) B(29) D(15) A(30) B(30) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30 105 DS21Q44 (LSB RS1 (30) C(16) D(16) RS2 (31) C(17) D(17) RS3 (32) C(18) D(18) RS3 (33) ...
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... B(28) D(14) A(29) B(29) D(15) A(30) B(30) NAME AND DESCRIPTION Spare Bits. Remote Alarm Bit (integrated and reported in SR1.6). Signaling Bit A for Channel 1 Signaling Bit D for Channel 30 105 DS21Q44 (LSB TS1 (40) C(16) D(16) TS2 (41) C(17) D(17) TS3 (42) C(18) D(18) TS4 (43) ...
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... Transmit Side Via the THSE control bit (CCR3.2), the DS21Q44 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The hardware signaling insertion capabilities of each framer are available whether the transmit side elastic store is enabled or disabled ...
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... T16S=1(TCR1.5) 11. PER–CHANNEL CODE GENERATION AND LOOPBACK Each framer in the DS21Q44 can replace data on a channel–by–channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 11.1. The receive direction is from the E1 line to the backplane and is covered in Section 11.2. ...
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... Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel TIDR4 TIDR3 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last 105 DS21Q44 (LSB) CH2 CH1 TIR1 (26) CH10 CH9 TIR2 (27) ...
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... TC register into the transmit data stream NAME AND DESCRIPTION MSB of the Code (this bit is sent first to the backplane) LSB of the Code (this bit is sent last to the backplane 105 DS21Q44 (LSB TC1 (60) (LSB) CH2 CH1 TCC1 (A0) CH10 ...
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... CH29 CH28 CH27 NAME AND DESCRIPTION Receive Channel Blocking Control Bits force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time 52 of 105 DS21Q44 (LSB) CH2 CH1 RCC1 (A4) CH10 CH9 RCC2 (A5) CH18 ...
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... Alignment Word and Spare/Remote Alarm bits. 13. ELASTIC STORES OPERATION Each framer in the DS21Q44 contains dual two–frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1 ...
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... RIR.6 and RIR.7 bits. 14. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION Each framer in the DS21Q44 provides for access to both the Sa and the Si bits via three different methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in Section 14 ...
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... RAF.4 1 RAF.3 0 RAF.2 1 RAF.1 1 RAF NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit Frame Alignment Signal Bit 105 DS21Q44 (LSB ...
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... Sa4 RNAF.4 Sa5 RNAF.3 Sa6 RNAF.2 Sa7 RNAF.1 Sa8 RNAF.0 TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB [Must be programmed with the seven bit FAS word; the DS21Q44 does not automatically set these bits] SYMBOL POSITION Si TAF.7 0 TAF.6 0 TAF.5 1 TAF.4 1 TAF.3 0 TAF ...
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... TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex) (MSB [Bit 2 must be programmed to one; the DS21Q44 does not automatically set this bit] SYMBOL POSITION Si TNAF.7 1 TNAF.6 A TNAF.5 Sa4 TNAF.4 Sa5 TNAF.3 Sa6 TNAF.2 Sa7 TNAF.1 Sa8 TNAF.0 14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received ...
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... TRA register into the transmit data stream. Additional Bit 4 Insertion Control Bit. 0=do not insert data from the TSa4 register into the transmit data stream. 1=insert data from the TSa4 register into the transmit data stream 105 FUNCTION (LSB) Sa6 Sa7 DS21Q44 Sa8 ...
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... Sa8 TSaCR.0 15. HDLC Controller for the Sa Bits or DS0 Each framer in the DS21Q44 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this operation is covered in Section 15.1. ...
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... HDLC controller access to 64–byte HDLC FIFO in receive direction controls the HDLC function when used on DS0 channels status information on transmit HDLC controller access to 64–byte HDLC FIFO in transmit direction controls the HDLC function when used on DS0 channels 60 of 105 DS21Q44 FUNCTION ...
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... This operation is key in controlling the DS21Q44 with higher–order software languages. Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR) ...
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... FIFO at THFR. The HDLC controller will clear this bit when the last byte has been transmitted. Transmit Zero Stuffer Defeat. Overrides internal enable enable the zero stuffer (normal operation disable the zero stuffer. Transmit CRC Defeat enable CRC generation (normal operation disable CRC generation 105 DS21Q44 (LSB) TEOM TZSD TCRCD ...
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... The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details 105 DS21Q44 (LSB) THALF TNF TMEND ...
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... Receive FIFO Not Empty interrupt masked interrupt enabled. Transmit FIFO Half Empty interrupt masked interrupt enabled. Transmit FIFO Not Full interrupt masked interrupt enabled. Transmit Message End interrupt masked interrupt enabled 105 DS21Q44 (LSB) THALF TNF TMEND ...
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... HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte 105 DS21Q44 (LSB) CBYTE OBYTE (LSB) HDLC1 HDLC0 ...
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... HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte 105 DS21Q44 (LSB) EMPTY TFULL TUDR (LSB) HDLC2 HDLC1 HDLC0 ...
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... RCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. DS0 Channel Select Bit 3. DS0 Channel Select Bit 2. DS0 Channel Select Bit 1. DS0 Channel Select Bit 0. LSB of the DS0 channel select 105 DS21Q44 (LSB) RD1 RD0 ...
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... Sa bits from the HDLC controller. TD0 to TD4 defines which Sa bits are to be routed. TD4 corresponds to Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8 route DS0 channels from the HDLC controller. TDC1.5 is used to determine how the DS0 channels are selected 105 DS21Q44 (LSB) RDB2 RDB1 (LSB) TD1 ...
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... The 8.192 MHz bus speed allows all four of the DS21Q44’s framers to share a common bus. Framers can interleave their data either on byte or frame boundaries. Framers that share a common bus must be configured through software and require several device pins to be connected together externally (see figures 16-1 & ...
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... In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 18-1 shows the DS21Q44 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus 2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are programmed as slave devices ...
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... TSER2 RSIG1 RSIG2 TSIG1 TSIG2 71 of 105 FRAMER 3 RSYSCLK3 TSYSCLK3 RSYNC3 TSSYNC3 RSER3 TSER3 RSIG3 TSIG3 SYSCLK SYNC INPUT RSER TSER RSIG TSIG Bus 2 FRAMER 3 RSYSCLK3 TSYSCLK3 RSYNC3 TSSYNC3 RSER3 TSER3 RSIG3 TSIG3 SYSCLK SYNC INPUT RSER TSER RSIG TSIG DS21Q44 ...
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... Boundary Scan Register Device Identification Register The JTAG feature is only available when the DS21Q44 feature set is selected (FMS = 0). The JTAG feature is disabled when the DS21Q44 is configured for emulation of the DS21Q43 (FMS = 1). Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins ...
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... The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Test-Logic-Reset Upon power up of the DS21Q44, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the DS21Q44 will operate normally. ...
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... JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low, will put the controller in the Run-Test-Idle state. With JTMS high, the controller will enter the Select-DR-Scan state 105 DS21Q44 ...
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... IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS21Q44 with their respective operational binary codes are shown in Table 17-1. 1 ...
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... SAMPLE/PRELOAD A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the DS21Q44 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS21Q44 to shift data into the boundary scan register via JTDI using the Shift-DR state. ...
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... DS21Q42 DS21Q44 HIGH Z All digital outputs of the DS21Q44 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. CLAMP All digital outputs of the DS21Q44 will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction ...
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... SPARE1 - RFSYNC0 O JTRST* I TCLK0 I TLCLK0 O TSYNC0.cntl - TSYNC0 I/O TLINK0 A6/ALE (AS) I INT* O TSYSCLK1 I TSER1 I TSSYNC1 I TSIG1 I TCHBLK1 O TPOS1 O TNEG1 O RLINK1 O RLCLK1 O RCLK1 I RNEG1 I RPOS1 I RSIG1 O RCHBLK1 O RSYSCLK1 FMS 105 DS21Q44 CONTROL BIT DESCRIPTION 0 = RSYNC0 an input 1 = RSYNC0 an output 0 = TSYNC0 an input 1 = TSYNC0 an output ...
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... MUX I TSYSCLK2 I TSER2 I TSSYNC2 I TSIG2 I TCHBLK2 O TPOS2 O TNEG2 O RLINK2 O RLCLK2 O RCLK2 I RNEG2 I RPOS2 I RSIG2 O VSS - VDD - RCHBLK2 O RSYSCLK2 I RSYNC2.cntl - RSYNC2 I/O RSER2 O JTDI I RFSYNC2 105 DS21Q44 CONTROL BIT DESCRIPTION 0 = RSYNC1 an input 1 = RSYNC1 an output 0 = TSYNC1 an input 1 = TSYNC1 an output 0 = RSYNC2 an input 1 = RSYNC2 an output ...
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... O RFSYNC3 O VSS - VDD - CLKSI I TCLK3 I TLCLK3 O TSYNC3.cntl - TSYNC3 I/O TLINK3 I BUS.cntl - D0 or AD0 I AD1 I AD2 I 105 DS21Q44 CONTROL BIT DESCRIPTION 0 = TSYNC2 an input 1 = TSYNC2 an output 0 = RSYNC3 an input 1 = RSYNC3 an output 0 = TSYNC3 an input 1 = TSYNC3 an output 0 = D0-D7 or AD0-AD7 are inputs 1 = D0-D7 or AD0-AD7 are outputs ...
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... DEVICE SCAN PIN REGISTER BIT 120 90 121 89 122 88 123 87 124 86 125 85 126 84 127 83 128 82 SYMBOL TYPE D3 or AD3 I AD4 I AD5 I AD6 I AD7 I/O TSYSCLK0 I TSER0 I TSSYNC0 I TSIG0 105 DS21Q44 CONTROL BIT DESCRIPTION ...
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... RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel CHANNEL 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 1 LSB Sa4 CHANNEL Sa4 Sa5 82 of 105 CHANNEL 2 LSB CHANNEL 2 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 2 Sa5 Note 5 Sa6 Sa7 Sa8 DS21Q44 ...
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... RSYNC is in the output mode (RCR1 RSYNC is in the input mode (RCR1 RCHBLK is programmed to block channel 1 4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1 CHANNEL 24/32 LSB MSB CHANNEL 32 LSB MSB CHANNEL 105 CHANNEL 1/2 MSB LSB F CHANNEL 1 LSB MSB CHANNEL Note 4 DS21Q44 ...
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... FR2 CH1 FR3 CH1 FR0 CH2 BIT DETAIL FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL C/D D 105 FR1 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FRAMER 1, CHANNEL 1 MSB LSB FRAMER 1, CHANNEL C/D D/B DS21Q44 ...
Page 85
... FR3 CH1-32 FR0 CH1-32 BIT DETAIL FRAMER 0, CHANNEL 1 MSB LSB FRAMER 0, CHANNEL C/D D 105 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FRAMER 0, CHANNEL 2 MSB LSB FRAMER 0, CHANNEL C/D D DS21Q44 ...
Page 86
... The F-bit position is ignored by the DS2154 CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 A MSB CHANNEL 1 A Sa4 Sa5 LSB Si 1 CHANNEL 1 Note 6 Don't Care CHANNEL 24 LSB MSB 86 of 105 CHANNEL 2 LSB MSB Sa6 Sa7 Sa8 MSB CHANNEL CHANNEL 1 LSB MSB F-Bit DS21Q44 ...
Page 87
... Notes: 1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 25, and during bit 1 of timeslot 26 CHANNEL 32 LSB MSB CHANNEL 111213141516 17 18 19202122232425262728293031 RCLK / RSYSCLK TCLK / TSYSCLK Timeslot 25 RSER/TSER RCHCLK/TCHCLK RCHBLK/TCHBLK 87 of 105 CHANNEL 1 LSB MSB CHANNEL detail Timeslot 26 LSB MSB DS21Q44 ...
Page 88
... FRAMER 0, CHANNEL 1 LSB MSB FRAMER 0, CHANNEL 1 A D 105 FR0 CH2 FR1 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FR1 CH2 FR2 CH2 FR3 CH2 FRAMER 1, CHANNEL 1 MSB LSB FRAMER 1, CHANNEL 1 A D/B B C/D DS21Q44 LSB D/B ...
Page 89
... BIT DETAIL FRAMER 0, CHANNEL 1 MSB LSB FRAMER 0, CHANNEL 1 A D 105 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FRAMER 0, CHANNEL 2 MSB LSB FRAMER 0, CHANNEL 2 A D/B B C/D DS21Q44 ...
Page 90
... DS21Q44 FRAMER SYNCHRONIZATION FLOWCHART Figure 18-14 RLOS = 1 Resync if RCR1 Increment CRC4 Sync Counter; CRC4SA = 0 Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) 8ms CRC4 Multiframe Search Time (if enabled via CCR1.0) Out CRC4SA = 1 CRC4 Sync Criteria Met ...
Page 91
... DS21Q44 TRANSMIT DATA FLOW Figure 18- 1/2/3 3 3.2 TNAF.0 ata S ource ( TNAF.5 / ould be tie and sho uld be tied for data prop erly sou rced from uto R em ote A larm if enabled w ill only overw rite bit 3 of tim eslo the lign F ram es if the alarm needs to be sent. ...
Page 92
... MIN TYP –1 –1 +4 105 (0ºC to 70ºC for DS21Q44T; 0ºC to +85ºC for DS21Q44TN) MAX UNITS 5.5 V +0 MAX UNITS 2.97 to 3.63V for DS21Q44T 2.97 to 3.63V for DS21Q44TN) MAX UNITS mA +1.0 µA 1.0 µ DS21Q44 NOTES =25ºC) A NOTES NOTES ...
Page 93
... V –40ºC to +85º MIN TYP t 200 CYC 100 EL 100 RWH t 50 RWS DHR 0 DHW t 15 ASL t 10 AHL t 20 ASD 30 ASH 10 ASED t 20 DDR 50 DSW 93 of 105 = 2.97 to 3.63V for DS21Q44T DD = 2.97 to 3.63V for DS21Q44TN) MAX UNITS DS21Q44 NOTES ...
Page 94
... Data Hold Time from either WR* or DS* Inactive Address Hold from either WR* or DS* inactive See Figures 19–4 to 19–7 for details. (0ºC to 70º –40ºC to +85º MIN TYP 105 = 2.97 to 3.63V for DS21Q44T; = 2.97 to 3.63V for DS21Q44TN) MAX UNITS DS21Q44 NOTES ...
Page 95
... RSYNC, RCHBLK, RFSYNC, RLCLK Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC See Figures 19-8 to 18-10 for details. Notes: 1. RSYSCLK = 1.544 MHz. 2. RSYSCLK = 2.048 MHz. (0ºC to 70º –40ºC to +85º 2.97 to 3.63V for DS21Q44TN) DD MIN TYP t 488 ...
Page 96
... Delay TCLK to TPOS, TNEG Valid Delay TCLK to TCHBLK, TCHBLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK See Figures 19–11 to 19–13 for details. Notes: 1. TSYSCLK = 1.544 MHz. 2. TSYSCLK = 2.048 MHz. (0ºC to 70º –40ºC to +85º 2.97 to 3.63V for DS21Q44TN) DD MIN TYP t 488 ...
Page 97
... INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 19-1 ALE PW t ASD WR* t ASD RD CS* t ASL AD0-AD7 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 19-2 ALE PW t ASD RD* t ASD WR CS* t ASL AD0-AD7 t CYC ASH t ASED DDR t AHL t CYC ASH t ASED AHL 97 of 105 DHR DHW t DSW DS21Q44 ...
Page 98
... AHL INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 19 A7, Address Valid FS0, FS1 WR* t1 CS* 0ns min. RD* ASH t ASED t CYC t RWS t DDR AHL t DSW Data Valid 5ns min. / 20ns max. 0ns min 75ns max 105 RWH t DHR DHW t5 t4 0ns min. DS21Q44 ...
Page 99
... DS* 0ns min Notes: 1. The signal DS is active high when emulating the DS21Q43 (FMS = 0ns min 75ns min. Data Valid 5ns min. / 20ns max 75ns max 75ns max 105 t8 10ns 10ns min. min. t4 0ns min 0ns min. t4 0ns min. DS21Q44 ...
Page 100
... MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 19 A7, Address Valid FS0, FS1 R/W* t1 CS* 0ns min. DS* 0ns min Notes: 1. The signal DS is active high when emulating the DS21Q43 (FMS = 1) 10ns min. 0ns min 75ns min 75ns min. . 100 of 105 10ns t7 t8 min. t4 0ns min. DS21Q44 ...
Page 101
... RCHBLK RFSYNC / RMSYNC 1 RSYNC RLCLK t D1 Sa4 to Sa8 Bit Position RLINK Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied. MSB of Channel 101 of 105 DS21Q44 ...
Page 102
... RECEIVE SYSTEM SIDE AC TIMING Figure 19 RSYSCLK t D3 RSER / RSIG t D4 RCHCLK RCHBLK SYNC RSYNC RSYNC N otes the output m ode ( 1 the input m ode ( 1 RECEIVE LINE INTERFACE AC TIMING Figure 19- RCLK RPOS, RNEG Channel 102 of 105 DS21Q44 ...
Page 103
... TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between TLCLK/TLINK and TSYNC is implied 103 of 105 DS21Q44 ...
Page 104
... TSS YNC N otes only sam pled on the falling edge hen the transm it side elastic store is enabled and TC H BLK are synchronous with hen the transm it side elastic store is enabled. TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 19- TCLK TPOS, TNEG 104 of 105 t CH DS21Q44 ...
Page 105
... TQFP Package Specifications 105 of 105 DS21Q44 ...