GMS87C1408D Hynix Semiconductor, GMS87C1408D Datasheet
GMS87C1408D
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GMS87C1408D Summary of contents
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June. 2001 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS81C1404 GMS81C1408 User’s Manual Ver 1.2 ...
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OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . ...
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GMS81C1404 / GMS81C1408 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 1. OVERVIEW 1.1 Description The GMS81C1404 and GMS81C1408 are an advanced CMOS 8-bit microcontroller with 4K/8K bytes of ROM. The Hynix semiconductor’s GMS81C1404 and GMS81C1408 are a powerful microcontroller which provides a highly ...
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GMS81C1404/GMS81C1408 1.3 Development Tools The GMS81C1404 and GMS81C1408 are supported by a full-featured macro assembler, an in-circuit emulator TM CHOICE-Dr . 1.4 Ordering Information ROM Size 4K bytes 8K bytes 4K bytes (OTP) 8K bytes (OTP Circuit Emulators ...
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BLOCK DIAGRAM PSW RESET System controller System Clock Controller Timing generator Xin Clock Generator Xout Watch-dog Timer Power Supply June. 2001 Ver 1.2 Accumulator ALU 8-bit Basic Interval Inte rrupt C ontroller Timer 8-bit 8-bit ...
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GMS81C1404/GMS81C1408 3. PIN ASSIGNMENT AN0 / AVref / RB0 PWM0 / COMP0 / RB4 PWM1 / COMP1 / RB5 SRDYIN / SRDYOUT / RC3 AN0 / AVref / RB0 PWM0 / COMP0 / RB4 PWM1 / COMP1 / RB5 SRDYIN ...
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PACKAGE DIAGRAM 28 SKINNY DIP 0.021 0 SOP June. 2001 Ver 1.2 1.375 1.355 0.055 0.045 0.708 0.608 0.019 0.013 TYP 0.050 GMS81C1404/GMS81C1408 unit: inch MAX MIN TYP 0.300 0.300 0.275 0 ~ 15° TYP 0.100 0.042 ...
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GMS81C1404/GMS81C1408 5. PIN FUNCTION V : Supply voltage Circuit ground. SS RESET: Reset the MCU Input to the inverting oscillator amplifier and input to IN the internal main clock operating circuit Output from ...
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PIN NAME Pin No RESET OUT RA0 (EC0) 25 RA1 (AN1) 26 RA2 (AN2) 27 RA3 (AN3) 28 RA4 (AN4) 1 RA5 (AN5) 2 RA6 (AN6) 3 RA7 ...
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GMS81C1404/GMS81C1408 6. PORT STRUCTURES • RESET Internal RESET • Xin, Xout STOP To System CLK • RA0/EC0 Data Bus Data Bus Data Bus Data Reg. Direction Reg. Read EC0 V DD Xout V SS Xin June. 2001 ...
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RA1/AN1 ~ RA7/AN7 Data Bus Data Bus Data Bus To A/D Converter Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM • RB0 / AN0 / AVref Data Bus AVREFS Data Bus Data Bus To A/D ...
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GMS81C1404/GMS81C1408 • RB1/BUZ, RB4/PWM0/COMP0, RB5/PWM1/COMP1, RB7/TMR2OV, RC6/SOUT PWM/COMP BUZ,TMR2OV,SOUT Data Reg. Data Bus Function Select Direction Reg. Data Bus Data Bus • RB2/INT0, RB3/INT1, RD0/INT2, RD1/INT3 Pull-up Select Data Bus Function Select Data Bus Data Bus INT0, INT1 INT2, INT3 ...
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RD2 Data Bus Data Bus Data Bus • RC5/SIN Data Bus Function Select Data Bus Data Bus • RC3 / SRDYIN / SRDYOUT, RC4 / SCKIN / SCKOUT SRDYOUT SCKOUT Data Reg. Data Bus Function Select Direction Reg. Data ...
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GMS81C1404/GMS81C1408 7. ELECTRICAL CHARACTERISTICS (GMS81C1404/GMS81C1408) 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (V ............................................................... -0 Maximum current out of V ...
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DC Electrical Characteristics (T =-20~85 C for GMS81C1404/1408 Parameter Symbol V IH1 V Input High Voltage IH2 V IH3 V IL1 V Input Low Voltage IL2 V IL3 Output High Voltage Output Low ...
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GMS81C1404/GMS81C1408 7.5 AC Characteristics (T =-20~85 C for GMS81C1404/1408 Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width RESET Input Width X IN RESET INT0, INT1 INT3 INT2, ...
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Typical Characteristics This graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified ...
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GMS81C1404/GMS81C1408 = (mA IH1 X , RESET IN V IH1 f =4MHz XIN (V) Ta= ...
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ELECTRICAL CHARACTERISTICS (GMS87C1404/GMS87C1408) 8.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (V ............................................................... -0 Maximum current out of V pin ...
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GMS81C1404/GMS81C1408 8.4 DC Electrical Characteristics (T =-20~ =2.5~5. Parameter Symbol V IH1 V Input High Voltage IH2 V IH3 V IL1 V Input Low Voltage IL2 V IL3 Output High Voltage Output ...
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AC Characteristics (T =-20~+ =5V 10 Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width RESET Input Width X IN RESET INT0, INT1 INT3 INT2, ...
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GMS81C1404/GMS81C1408 8.6 Typical Characteristics This graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside ...
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= (mA IH1 X , RESET IN V IH1 f =4MHz XIN (V) Ta= ...
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GMS81C1404/GMS81C1408 9. MEMORY ORGANIZATION The GMS81C1404 and GMS81C1408 have separate ad- dress spaces for Program memory and Data Memory. Pro- gram memory can only be read, not written to. It can be up 9.1 Registers This device has six registers ...
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NEGATIVE FLAG OVERFLOW FLAG BRK FLAG [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to “0”. This flag immedi- ately becomes “0” when ...
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GMS81C1404/GMS81C1408 9.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 4K/8K bytes program memory space only physically implemented. Accessing a location above FFFF will cause a wrap-around to 0000 H ...
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Address PCALL Area Memory 0FF00 H 0FFFF H PCALL rel 4F35 PCALL 35H 0FF00H 0FF35H NEXT 0FFFFH June. 2001 Ver 1.2 PCALL Area (256 Bytes) Figure 9-6 PCALL and TCALL Memory Area TCALL ...
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GMS81C1404/GMS81C1408 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED DW NOT_USED DW SPI_INT DW BIT_INT DW WDT_INT DW AD_INT DW TMR3_INT DW TMR2_INT DW INT3 DW INT2 DW TMR1_INT DW TMR0_INT DW ...
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Data Memory Figure 9-7 shows the internal Data Memory space availa- ble. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. 0000H USER MEMORY (including STACK) 00BFH 00C0H CONTROL REGISTERS 00FFH Figure 9-7 ...
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GMS81C1404/GMS81C1408 1. “byte, bit” means that register can be addressed by not only bit but byte manipulation instruction. 2. “byte” means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write ...
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Address Name Bit 7 C0H RA RA Port Data Register C1H RAIO RA Port Direction Register C2H RB RB Port Data Register C3H RBIO RB Port Direction Register C4H RC RC Port Data Register C5H RCIO RC Port Direction Register ...
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GMS81C1404/GMS81C1408 EAH ADCM - EBH ADCR ADC Result Data Register 1 ECH Basic Interval Timer Data Register BITR 1 ECH - CKCTLR EDH WDTR WDTCL 2 EFH - PFDR Table 9-3 Control Registers of GMS81C1404 and GMS81C1408 These registers of ...
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Addressing Mode The GMS81C1404 and GMS81C1408 uses six addressing modes; • Register addressing • Immediate addressing • Direct page addressing • Absolute addressing • Indexed addressing • Register-indirect addressing (1) Register Addressing Register addressing accesses the ...
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GMS81C1404/GMS81C1408 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 983500 INC !0035H 0035 data 0F100 98 H 0F101 35 H address: 0035 0F102 00 ...
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Y indexed direct page (8 bit offset) This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of ...
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GMS81C1404/GMS81C1408 Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect page plus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H ...
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I/O PORTS The GMS81C1404 and GMS81C1408 has four ports, RA, RB, RC and RD. These ports pins may be multiplexed with an alternate function for the peripheral features on the de- vice. In general, when a initial reset state, ...
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GMS81C1404/GMS81C1408 10.2 RB and RBIO registers 5-bit bidirectional I/O port (address C2 pin can be set individually as input and output through the RBIO register (address addition, Port RB is mul- H tiplexed with ...
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June. 2001 Ver 1.2 PORT RBFUNC.4~0 0 RB7 (Normal I/O Port) RB7/ TMR2OV 1 Timer2 Overflow Output 0 RB6 (Normal I/O Port) RB6/EC1 1 Event Counter 1 Input 0 RB5 (Normal I/O Port) RB5/ PWM1/ PWM1 Output / 1 COMP1 ...
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GMS81C1404/GMS81C1408 10.3 RC and RCIO registers 4-bit bidirectional I/O port (address C4 pin can be set individually as input and output through the RCIO register (address addition, Port RC is multiplexed with Serial ...
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RD and RDIO registers 3-bit bidirectional I/O port (address C6 pin can be set individually as input and output through the RD Data Register ADDRESS : C6H RD RESET VALUE : Undefined RD Direction Register ADDRESS ...
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GMS81C1404/GMS81C1408 11. CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and pe- ripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic ...
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Basic Interval Timer The GMS81C1404 and GMS81C1408 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 12-1 .The 8-bit Basic interval timer reg- ister (BITR) is increased every internal count ...
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GMS81C1404/GMS81C1408 13. TIMER / COUNTER The GMS81C1404 and GMS81C1408 has four Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the ...
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CAP0 CAP1 PWME The value “0” or “1” corresponding your operation. 13.1 ...
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GMS81C1404/GMS81C1408 These timers have each 8-bit count register and data regis- ter. The count register is increased by every internal or ex- ternal clock input. The internal clock has a prescaler divide ratio option 32,128, 512, ...
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Timer/Counter Mode The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000 matches TDR0, TDR1 and then resets to 0000 match output generates Timer 0 interrupt not Timer ...
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GMS81C1404/GMS81C1408 timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 13-8 ...
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T0 Ext. INT0 Pin Interrupt Request (INT0F) Ext. INT0 Pin Interrupt Request (INT0F) Ext. INT0 Pin Interrupt Request (INT0F) Interrupt Request (T0F) T0 June. 2001 Ver 1.2 n Interrupt Interval ...
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GMS81C1404/GMS81C1408 13.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by ...
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If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution T1CK[1:0] = T1CK[1:0] = 00(125nS) 01(250nS) 10-bit 7.8KHz 3.9KHz 9-bit 15.6KHz 7.8KHz 8-bit 31.2KHz 15.6KHz 7-bit 62.5KHz 31.2KHz Table 13-2 PWM Frequency vs. Resolution at ...
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GMS81C1404/GMS81C1408 fxin PWM POL=1 PWM POL=0 Duty Cycle [80H x 125nS = 16uS] Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz] T1CK[1: (fxin) PWM0HR = 0CH T1PPR = FFH T1PDR = 80H T ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI) module is a serial in- terface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be SPI Mode Control Register POL SRDY SIOM POL Serial Clock Polarity ...
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GMS81C1404/GMS81C1408 The SPI allows 8-bits of data to be synchronously transmit- ted and received. To accomplish communication, typically three pins are used: - Serial Data In RC5/SIN - Serial Data Out RC6/SOUT - Serial Clock RC4/SCK Additonarlly a fourth pin ...
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Buzzer Output function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable ...
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GMS81C1404/GMS81C1408 16. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output ...
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A/D Control Register - - ADCM Reserved A/D Result Data Register ADCR7 ADCR6 ADCR ENABLE A/D CONVERTER A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT A/D START (ADST = 1) NOP ADSF = 1 YES READ ADCR Figure 16-3 A/D Converter ...
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GMS81C1404/GMS81C1408 (3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conver- sion is performed with any of pins AN0 to AN7 selected, ...
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INTERRUPTS The GMS81C1404 and GMS81C1408 interrupt circuits consist of Interrupt enable register (IENH, IENL), Inter- rupt request flags of IRQH, IRQL, Interrupt Edge Selec- tion Register (IEDS), priority circuit and Master enable flag(“I” flag of PSW). The configuration of ...
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GMS81C1404/GMS81C1408 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers ...
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Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” reset or an in- struction. Interrupt acceptance sequence requires =4MHz) after the ...
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GMS81C1404/GMS81C1408 The following method is used to save/restore the general- purpose registers. Example: Register save using push and pop instructions INTxx: PUSH A ;SAVE ACC. PUSH X ;SAVE X REG. PUSH Y ;SAVE Y REG. interrupt processing POP Y ;RESTORE ...
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Main Program service TIMER 1 service enable INT0 disable other EI Occur Occur TIMER1 interrupt INT0 enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting ...
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GMS81C1404/GMS81C1408 17.4 External Interrupt The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0E6 ) as shown in Figure 17 The edge detection of external interrupt ...
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Interrupt Interrupt goes latched active June. 2001 Ver 1 OSC OSC Interrupt processing Figure 17-7 Interrupt Response Timing Diagram GMS81C1404/GMS81C1408 Interrupt routine 63 ...
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GMS81C1404/GMS81C1408 18. WATCHDOG TIMER The purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. The watchdog timer has two ...
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Power Saving Mode For applications where power consumption is a critical factor, device provides two kinds of power saving func- tions, STOP mode and Wake-up Timer mode. The power saving function is activated by execution of Peripheral RAM Control ...
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GMS81C1404/GMS81C1408 Release the STOP mode The exit from STOP mode is hardware reset or external in- terrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to ...
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Oscillator (X pin) IN Internal Clock RESET Internal RESET 19.2 STOP Mode using Internal RCWDT In the STOP mode using Internal RC-Oscillated Watchdog Timer, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The ...
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GMS81C1404/GMS81C1408 Oscillator (X pin) IN Internal RC Clock Internal Clock External Interrupt (or WDT Interrupt) BIT N-1 N N-2 Counter Normal Operation Figure 19-4 STOP Mode Releasing by External Interrupt or WDT Interrupt(using RCWDT) Oscillator (X pin) IN Internal RC ...
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Note: After STOP instruction, at least two or more NOP in- struction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP In addition, the clock source of timer0 and timer2 should be selected to 2048 devided ...
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GMS81C1404/GMS81C1408 INPUT PIN internal pull- GND X Weak pull-up current flows Figure 19-7 Application Example of Unused Input Port OUTPUT PIN ON OFF i GND X In the left case, much current flows from port to GND. ...
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RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms ...
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GMS81C1404/GMS81C1408 21. POWER FAIL PROCESSOR The GMS81C1404 and GMS81C1408 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/ programmed) or disable (if set) the Power-fail Detect cir- cuitry. If ...
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V DD Internal RESET V DD When PFDM = 1 Internal RESET V DD Internal RESET V DD System Clock When PFDM = System Clock June. 2001 Ver 1.2 t < 64mS Figure 21-3 Power Fail Processor ...
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GMS81C1404/GMS81C1408 22. OTP PROGRAMMING (GMS87C1404/GMS87C1408 only) 22.1 DEVICE CONFIGURATION AREA The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as secu- rity bit. Ten memory locations (0F50 ~ 0FE0 H 0F50 H DEVICE CONFIGURATION ...
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User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RB0 (AVref/AN0) 7 RB1 (INT0) 8 RB2 (INT1) 9~18 RB3~7, RC3~6, RD2 OUT ...
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GMS81C1404/GMS81C1408 T SET1 EPROM Enable T VPPS VDDS CTL0 0V 0V CTL1 CTL2 0V A_D7~ A_D0 V DD1H V DD Figure 22-3 Timing Diagram in Program (Write & Verify) Mode T SET1 EPROM Enable T VPPS ...
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Parameter Programming Supply Current Supply Current in EPROM Mode V Level during Programming PP V Level in Program Mode DD V Level in Read Mode DD CTL2~0 High Level in EPROM Mode CTL2~0 Low Level in EPROM Mode A_D7~A_D0 High ...
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GMS81C1404/GMS81C1408 START Set Set Verify blank First Address Location Next address location N=1 EPROM Write 100uS program time Verify pass Apply 3N program cycle NO Last address 78 DD1H Report IHP Programming failure NO ...
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June. 2001 Ver 1.2 START Set V =V DD2H DD Set V =V IHP PP First Address Location Next address location NO Last address YES Report Read =0V PP END Figure 22-6 Reading Flow Chart ...
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APPENDIX ...
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A. INSTRUCTION MAP 00000 00001 00010 00011 LOW HIGH SET1 BBS BBS 000 - dp.bit A.bit,rel dp.bit,rel 001 CLRC 010 CLRG 011 DI 100 CLRV 101 SETC 110 SETG 111 EI 10000 10001 10010 10011 LOW ...
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GMS81C1404/GMS81C1408 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC 1 ADC #imm 2 ADC dp 3 ADC ADC !abs 5 ADC !abs + Y 6 ADC [ ADC [ dp ...
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NO. MNEMONIC 45 EOR #imm 46 EOR dp 47 EOR EOR !abs 49 EOR !abs + Y 50 EOR [ EOR [ EOR { X } ...
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GMS81C1404/GMS81C1408 2. REGISTER / MEMORY OPERATION NO. MNEMONIC 1 LDA #imm 2 LDA dp 3 LDA LDA !abs 5 LDA !abs + Y 6 LDA [ LDA [ ...
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OPERATION NO. MNEMONIC 1 ADDW dp 2 CMPW dp 3 DECW dp 4 INCW dp 5 LDYA dp 6 STYA dp 7 SUBW dp 4. BIT MANIPULATION NO. MNEMONIC 1 AND1 M.bit 2 AND1B M.bit 3 BIT dp ...
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GMS81C1404/GMS81C1408 5. BRANCH / JUMP OPERATION NO. MNEMONIC 1 BBC A.bit,rel 2 BBC dp.bit,rel 3 BBS A.bit,rel 4 BBS dp.bit,rel 5 BCC rel 6 BCS rel 7 BEQ rel 8 BMI rel 9 BNE rel 10 BPL rel 11 BRA ...
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CONTROL OPERATION & etc. NO. MNEMONIC 1 BRK NOP 5 POP A 6 POP X 7 POP Y 8 POP PSW 9 PUSH A 10 PUSH X 11 PUSH Y 12 PUSH PSW 13 ...
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... MM DD This box is written after “5.Verification” Approval Date: I agree w ith your verification data and confirm you to m ake m ask set. Tel: Name & Signature: Hynix Semiconductor 28SKDIP 28SOP YES NO HIGH LOW File Name: ( .OTP) Check Sum: ( 0000H Set “00” in ...
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... MM DD This box is written after “5.Verification” Approval Date: I agree w ith your verification data and confirm you to m ake m ask set. Tel: Name & Signature: Hynix Semiconductor 28SKDIP 28SOP YES NO HIGH LOW File Name: ( .OTP) Check Sum: ( 0000H Set “00” in ...
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... MM DD This box is written after “5.Verification” Approval Date: I agree w ith your verification data and confirm you to m ake m ask set. Tel: Name & Signature: Hynix Semiconductor 28SKDIP 28SOP YES NO HIGH LOW File Name: ( .OTP) Check Sum: ( 0000H Set “00” in ...
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... MM DD This box is written after “5.Verification” Approval Date: I agree w ith your verification data and confirm you to m ake m ask set. Tel: Name & Signature: Hynix Semiconductor 28SKDIP 28SOP YES NO HIGH LOW File Name: ( .OTP) Check Sum: ( 0000H Set “00” in ...