SMJ44C251B-10JDM Austin Semiconductor, Inc., SMJ44C251B-10JDM Datasheet

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SMJ44C251B-10JDM

Manufacturer Part Number
SMJ44C251B-10JDM
Description
Manufacturer
Austin Semiconductor, Inc.
Datasheet
256K X 4 VRAM
256K x 4 DRAM
with 512K x 4 SAM
AVAILABLE AS MILITARY
• SMD 5962-89497
• MIL-STD-883
FEATURES
OPTIONS
• Timing
• Package(s)
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
SPECIFICATIONS
Serial-Data Register
Class B High-Reliability Processing
SAM: 512 Words × 4 Bits
On-Chip Color Register
Write-Per-Bit Modes to Simplify System Design
512 Selectable Serial-Register Starting
Split Serial-Data Register for Simplified Real-Time Register Reload
Single 5-V Power Supply (±10% Tolerance)
Dual Port Accessibility–Simultaneous and Asynchronous Access
From the DRAM and SAM Ports
as Four Memory Address Locations Written per Cycle From an
Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Enhanced Page-Mode Operation for Faster Access
CAS-Before-RAS (CBR) and Hidden Refresh Modes
All Inputs/Outputs and Clocks Are TTL Compatible
Long Refresh Period: Every 8 ms (Max)
3-State Serial I/Os Allow Easy Multiplexing of Video-Data
DRAM: 262144 Words × 4 Bits
Bidirectional-Data-Transfer Function Between the DRAM and the
4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many
Up to 33-MHz Uninterrupted Serial-Data Streams
Streams
100ns, 30ns/27ns
120ns, 35ns/35ns
Ceramic SOJ
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flat Pack
Ceramic ZIP
Ceramic LCC
For more products and information
www.austinsemiconductor.com
please visit our web site at
Austin Semiconductor, Inc.
MT Prefix
MARKING
DCJ
EC
CZ
---
C
F
-10
-12
SMJ Prefix
HMM
SVM
JDM
HJM
---
---
1
ME\/WE\
TR\/OE\
SDQ1
SDQ2
RAS\
SDQ0 - SDQ3 SDQ1 - SDQ4 Serial Data In-Out
DQ1
DQ2
Vcc
28-Pin DIP (C)
NC
PIN NAME
DQ0 - DQ3
A8
A6
A5
A4
SC
A0 - A8
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
(SMJ)
(400 MIL)
TRG\
CAS\
RAS\
GND
DSF
QSF
Vcc
Vss
SE\
SC
W\
ME\/WE\
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TR\/OE\
SDQ1
SDQ2
RAS\
DQ1
DQ2
Vcc
NC
A8
A6
A5
A4
SC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ1 - DQ4
PIN NAME
ME\ /WE\
PIN ASSIGNMENT
TR\ /OE\
A0 - A8
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
CAS\
RAS\
(MT)
DSF
QSF
SE\
Vcc
Vss
NC
SC
28-Pin ZIP (CZ)
SDQ2
SDQ0
TRG\
GND
DQ3
DQ1
28-Pin FP (F)
(Top View)
DSF
Vcc
QSF
Vss
A8
A5
A3
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Address Inputs
Column Enable
DRAM Data In-Out/Write-Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Transfer Register/Q Output Enable
Write-Mask Select/Write Enable
Special Function Select
Split-Register Activity Status
5V Supply
Ground
Ground (Important: Not Connected to
internal Vss, Pin should be left open or
tied to ground.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
10
12
14
16
18
20
22
24
26
28
ME\/WE\
2
4
6
8
TR\/OE\
SMJ44C251B
SDQ1
SDQ2
DQ2
SE\
SDQ3
SC
SDQ1
DQ0
W\
RAS\
A8
A4
A7
A2
A0
CAS\
RAS\
DQ1
DQ2
Vcc
NC
A8
A6
A5
A4
SC
28-Pin SOJ (DCJ)
28-Pin LCC (EC)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DESCRIPTION
MT42C4256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VRAM
VRAM
VRAM
VRAM
VRAM
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vss
SDQ4
SDQ3
SE\
DQ4
DQ3
DSF
CAS\
QSF
A0
A1
A2
A3
A7

Related parts for SMJ44C251B-10JDM

SMJ44C251B-10JDM Summary of contents

Page 1

... SDQ0 - SDQ3 SDQ1 - SDQ4 Serial Data In-Out TRG\ W\ DSF QSF Vcc Vss GND Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 PIN ASSIGNMENT (Top View) 28-Pin SOJ (DCJ) 28-Pin LCC (EC) Vss SDQ4 2 27 SDQ1 SDQ3 ...

Page 2

... A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the split-register mode. All inputs, outputs, and clock signals on the SMJ44C251B/ MT42C4256 are compatible with Series 54 TTL devices. All ad- dress lines and data-in lines are latched on-chip to simplify system design ...

Page 3

... Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM SMJ44C251B/MT42C4256 Rev. 0.1 12/03 SMJ44C251B Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 VRAM VRAM VRAM VRAM VRAM MT42C4256 ...

Page 4

... Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 CAS\ ADDRESS DQ0 - DQ3 FALL RAS\ CAS\ DSF RAS\ CAS Row Tap X X Addr Point Row Tap X X Addr Point Refresh Tap X X Addr ...

Page 5

... In DRAM operation, W\ enables data to be written to the DRAM also used to select the DRAM write-per-bit mode. Holding W\ low on the falling edge of RAS\ invokes the write- per-bit operation. The SMJ44C251B/MT42C4256 supports both the normal write-per-bit mode and the persistent write-per-bit mode. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ...

Page 6

... SERIAL CLOCK (SC) Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B/MT42C4256 is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static ...

Page 7

... Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B/MT42C4256 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS\ transitions low. A valid column address can be presented immediately after SMJ44C251B/MT42C4256 Rev ...

Page 8

... The write-per-bit operation is invoked only when W\ is held low on the falling edge of RAS held high on the falling edge of RAS\, write-per-bit is not enabled and the write operation is performed to all four DQs. The SMJ44C251B/ MT42C4256 offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent write-per-bit mode. ...

Page 9

... Refresh address 2. Row address 3. Block address (A2 –A8) 4. Color-register data 5. Column-mask data 6. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS\. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 SMJ44C251B Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 VRAM VRAM VRAM VRAM VRAM ...

Page 10

... Austin Semiconductor, Inc. FIGURE 3: BLOCK-WRITE CIRCUIT BLOCK DIAGRAM FIGURE 4: EXAMPLE OF BLOCK WRITE OPERATION WITH DQ MASK AND ADDRESS MASK SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 11

... RAS\, determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random and the serial interfaces. As shown in the “Transfer-Operation Functions” table, the SMJ44C251B/MT42C4256 supports five basic modes of transfer operation: Register-to-memory transfer (normal write transfer, • ...

Page 12

... RAS\ to select one of the 512 rows available for transfer. The nine column- Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 CAS\ ADDRESS DQ0 - DQ3 FALL DSF RAS\ CAS\ ...

Page 13

... Each of these offers the flexibility of controlling the TRG\ trailing edge in the read-transfer cycle (see Figure 7). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 14

... QSF. In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is reached (see Figure 8 and Figure 9). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 15

... Figure 11, Case I). If there is no split-register read transfer to the inactive half during this period, the serial pointer points next to bit 256 or bit 0, respectively (see Figure 11, Case II). Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 16

... A MIN NOM 4 2.9 -1 -55 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 MAX UNIT 5 6.5 V 0.6 V 125 °C 125 °C ...

Page 17

... CC6A NOTES: 1. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designer’s Handbook. This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ terminals are switched. This may cause V and V to exceed the data-book limit for a short period of time, depending upon output loading and temperature ...

Page 18

... SCA 30pF a(SE) SEA 100pF dis(CH) OFF 100pF dis(G) OEZ 30pF dis(SE) SEZ L Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 18 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 UNIT -10 -12 4 MIN MAX MIN MAX 100 120 UNIT ...

Page 19

... RCS t /t su(WCL) WCS t /t su(WCH) CWL t /t su(WRH) RWL Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 19 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 -10 -12 MAX MIN MAX UNIT 220 ns 220 ns 290 125 ns 220 ns 220 ns ...

Page 20

... RCD t /t d(CARH) RAL d(RLWL) RWD d(CAWL) AWD d(RLCH)RF CHR d(CLRL)RF CSR d(RHCL)RF RPC t d(CLGH) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 20 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 -10 -12 MIN MAX MIN MAX UNIT ...

Page 21

... SDD d(GLRH) ROH t 25 d(MSRL d(SCQSF) SQD t /t d(CLQSF) CQD d(GHQSF) TQD d(RLQSF) RQD REF Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 21 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 -10 -12 MAX MIN MAX UNIT 140 - w(RH ...

Page 22

... Depending on the user’s transition times, this may require additional RAS\ low su(WRH) is set to t min as a reference. d(RLCL) d(RLCL) applies only when the SAM was previously in serial-input mode. d(SCRL) FIGURE 12: LOAD CIRCUIT Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 22 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 23

... Austin Semiconductor, Inc. FIGURE 13: Read-Cycle Timing SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 23 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 24

... Load write mask on later of W\ fall and CAS\ fall SMJ44C251B/MT42C4256 Rev. 0.1 12/03 STATE Don't Care Write Mask Valid Data Don't Care Don't Care Write Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 24 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 5 Valid Data Valid Data ...

Page 25

... Load write mask on later of W\ fall and CAS\ fall SMJ44C251B/MT42C4256 Rev. 0.1 12/03 STATE Don't Care Write Mask Valid Data Don't Care Don't Care Write Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 25 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 5 Valid Data Valid Data ...

Page 26

... Load write mask on later of W\ fall and CAS\ fall SMJ44C251B/MT42C4256 Rev. 0.1 12/03 STATE Don't Care Write Mask Valid Data Don't Care Don't Care Write Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 26 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 5 Valid Data Valid Data ...

Page 27

... DSF is selected on the falling edges of RAS\ and CAS\ to select the desired write mode (normal, block write, etc.) SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 27 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 28

... RAS\. h(TRG) STATE Don't Care Write Mask Valid Data Don't Care Don't Care Write Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 28 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 5 Valid Data Valid Data ...

Page 29

... Load write mask on later of W\ fall and CAS\ fall SMJ44C251B/MT42C4256 Rev. 0.1 12/03 STATE Don't Care Write Mask Valid Data Don't Care Don't Care Write Mask Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 29 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 5 Valid Data Valid Data ...

Page 30

... Austin Semiconductor, Inc. FIGURE 20: Load-Color-Register-Cycle Timing SMJ44C251B/MT42C4256 Rev. 0.1 12/03 (Early-Write Load) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 30 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 31

... Austin Semiconductor, Inc. FIGURE 21: Load-Color-Register-Cycle Timing SMJ44C251B/MT42C4256 Rev. 0.1 12/03 (Delayed-Write Load) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 31 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 32

... Don't Care Column Mask L H Don't Care Column Mask DQ0 — column 0 (address DQ1 — column 1 (address DQ2 — column 2 (address DQ3 — column 3 (address Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 32 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 ...

Page 33

... Don't Care Column Mask L H Don't Care Column Mask DQ0 — column 0 (address DQ1 — column 1 (address DQ2 — column 2 (address DQ3 — column 3 (address Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 33 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 4 ...

Page 34

... DQ3 — column 3 (address Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 34 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 from the falling edge of RAS\. h(TRG) STATE 3 4 Write Mask Column Mask Don't Care Column Mask ...

Page 35

... FIGURE 25: RAS\-Only Refresh-Cycle Timing NOTES: NOTE E: In persistent write-per-bit function, W\ must be high at the falling edge of RAS\ during the refresh cycle. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 35 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 36

... FIGURE 26: CBR-Refresh-Cycle Timing NOTES: NOTE F: In persistent write-per-bit operation, W\ must be high at the falling edge of RAS\ during the refresh cycle. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 36 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 37

... Austin Semiconductor, Inc. FIGURE 27: Hidden-Refresh-Cycle Timing SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 37 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 38

... NOTE G: The write-mode-control cycle is used to change the SDQs from the output mode to the input mode. This allows serial data to be written into the data register. This figure assumes that the device was originally in the serial-read mode. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 38 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 39

... Austin Semiconductor, Inc. FIGURE 29: Data-Register-to-Memory Transfer Timing, SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Serial Input Enable Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 39 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 40

... Austin Semiconductor, Inc. FIGURE 30: Alternate Data-Register-to-Memory SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Transfer-Cycle Timing Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 40 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 41

... Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Early-Load Operation min < t < min. h(TRG) h(TRG) d(RLTH Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 41 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 42

... Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 < 0 ns. d(THRH) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 42 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 43

... Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 < 0 ns. d(THRH) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 43 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 44

... Austin Semiconductor, Inc. FIGURE 34: Split-Register-Mode Read-Transfer-Cycle Timing SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 44 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 45

... Rev. 0.1 12/03 is met the minimum delay time between the rising edge d(MSRL) d(MSRL) requirement the minimum delay time between the d(RHMS) d(RHMS) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 45 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 d(MSRL) ...

Page 46

... NOTE T: While accessing data in the serial-data registers, the state of TRG don’t care as long as TRG\ is held high when RAS\ goes low to prevent data transfers between memory and data registers. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 46 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ) IL ...

Page 47

... NOTE V: While accessing data in the serial-data registers, the state of TRG don’t care as long as TRG\ is held high when RAS\ goes low to prevent data transfers between memory and data registers. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 47 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 48

... Any transfer-write cycles occurring between the transfer-read cycle and the subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 48 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ) IL ...

Page 49

... SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 49 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 50

... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #500 (Package Designator DCJ) SMD 5962-89497, Case Outline T *All measurements are in inches. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 50 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 51

... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #109 (Package Designator C or JDM) SMD 5962-89497, Case Outline X *All measurements are in inches. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 51 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 52

... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* SMD 5962-89497, Case Outline Y *All measurements are in inches. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Package Designator HJM Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 52 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 53

... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #203 (Package Designator EC or HMM) SMD 5962-89497, Case Outline Z *All measurements are in inches. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 53 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 54

... Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* Package Designator CZ or SVM SMD 5962-89497, Case Outline M *All measurements are in inches. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 54 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 ...

Page 55

... D --- E 0.380 E1 --- E2 0.180 E3 0.030 e 0.050 BSC L 0.250 Q 0.026 S1 0.000 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 55 VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 MAX 0.130 0.022 0.009 0.740 0.420 0.440 --- --- 0.370 0.045 --- ...

Page 56

... DCJ EXAMPLE: MT42C4256EC-10/883C Device Package Number Type MT42C4256 EC MT42C4256 EC EXAMPLE: MT42C4256CZ-12/883C Device Package Number Type MT42C4256 CZ MT42C4256 CZ EXAMPLE: SMJ44C251B 10HJM Device Speed ns Number SMJ44C251B 10 SMJ44C251B 12 EXAMPLE: SMJ44C251B 12HMM Device Speed ns Number SMJ44C251B 10 SMJ44C251B 12 *OPERATING TEMPERATURE XT = Military Temperature Range IT = Industrial Temperature Range ...

Page 57

... Austin Semiconductor, Inc. ASI TO DSCC PART NUMBER Package Designator C or JDM ASI Part Number SMD Part Number MT42C4256C-10/883C 5962-8949704MXA MT42C4256C-12/883C 5962-8949703MXA SMJ44C251B-10JDM** 5962-8949704MXA SMJ44C251B-12JDM** 5962-8949703MXA Package Designator EC or HMM ASI Part Number SMD Part Number MT42C4256EC-10/883C 5962-8949704MZA MT42C4256EC-12/883C 5962-8949703MZA SMJ44C251B-10HMM** 5962-8949704MZA ...

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