HY57V161610DTC-8 Hynix Semiconductor, HY57V161610DTC-8 Datasheet
HY57V161610DTC-8
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HY57V161610DTC-8 Summary of contents
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... Internal two banks operation ORDERING INFORMATION Part No. HY57V161610DTC-5 HY57V161610DTC-55 HY57V161610DTC-6 HY57V161610DTC-7 HY57V161610DTC-8 HY57V161610DTC-10 HY57V161610DTC-15 Note : 1. V (min) of HY57V161610DTC-5/55 is 3.15V DD This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied Rev ...
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PIN CONFIGURATION DQ0 DQ0 DQ1 DQ1 V V SSQ SSQ DQ2 DQ2 DQ3 DQ3 V V DDQ DDQ DQ4 DQ4 DQ5 DQ5 V V SSQ SSQ DQ6 DQ6 DQ7 DQ7 VDDQ VDDQ LDQM LDQM /WE /WE ...
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FUNCTIONAL BLOCK DIAGRAM 1Mx16 Synchronous DRAM Self Refresh Counter Refresh Interval Timer Address[0:10] CLK Precharge CKE Row Active BA(A11) Column Active CS RAS CAS WE UDQM LDQM Mode Register Rev. 4.0/Aug. 02 Refresh Counter Sense AMP & I/O gates Address ...
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... Output load capacitance for access time measurement Note : 1. Output load to measure access times is equivalent to two TTL gates and one capacitance(30pF). For details, refer to AC/DC output load circuit (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns (min) of HY57V161610DTC-5/55 is 3.15V‘ DD Rev. 4.0/Aug. 02 ...
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... Input leakage current IL Output leakage current IO Output high voltage V OH Output low voltage V OL Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3 3.6V, All other pins are not under test = 0V IN 4.D is disabled 3.6V OUT OUT Rev ...
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... IDD5 tRRC t tRRC(min), All banks active Self Refresh Current IDD6 CKE Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3.I and I depend on output loading and cycle rates. Specified values are measured with the output open. ...
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AC CHARACTERISTICS (TA=0qC to 70qC, V Parameter Symbol CL=3 tCK3 System clock CL=2 tCK2 cycle time CL=1 tCK1 Clock high pulse width tCHW Clock low pulse width tCLW CL=3 tAC3 Access time CL=2 tAC2 from clock CL=1 tAC1 Data-out hold ...
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... CLK to data output in high Z-time Note : 1.V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V DD 3.tCK2 is 8.9ns only when tAC2 is 7.9ns in HY57V161610DTC-6 and HY57V161610DTC-7. 4.Assume (input rise and fall time ) is 1ns. Rev. 4.0/Aug. 02 Note1,2 =3.0V to3.6V ...
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AC CHARACTERISTICS (TA=0qC to 70qC, V Paramter Symbol Operation RAS cycle time Auto Refresh tRRC RAS to CAS delay tRCD RAS active time tRAS RAS precharge time RAS to RAS bank active delay tRRD CAS to CAS bank active delay ...
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... Precharge to data output Hi-Z Power down exit time Self refresh exit time Refresh Time Note : 1. V (min) is 3.15V when HY57V161610DTC-7 operates at CAS latency=2 and tCK2=8.9ns. DD 2.V (min) of HY57V161610DTC-5/55 is 3.15V new command can be given tRRC after self refresh exit. DEVICE OPERATING OPTION TABLE ...
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... HY57V161610DTC-6 CAS Latency 166MHz 3CLKs 143MHz 3CLKs 125MHz 3CLKs HY57V161610DTC-7 CAS Latency 143MHz 3CLKs 125MHz 3CLKs 100MHz 2CLKs HY57V161610DTC-8 CAS Latency 125MHz 3CLKs 100MHz 3CLKs 83MHz 2CLKs HY57V161610DTC-10 CAS Latency 100MHz 3CLKs 83MHz 2CLKs HY57V161610DTC-15 CAS Latency 66MHz 1CLKs Rev ...
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COMMAND TRUTH TABLE Command CKEn-1 Mode Register Set No Operation Bank Active Read Read with Auto precharge Write Write with Auto precharge Precharge All Bank Precharge selected Bank Burst Stop U/LDQM Auto Refresh Burst-READ-Single-WRITE Entry 1 Self Refresh Exit Entry ...
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PACKAGE INFORMATION 400mil 50pin Thin Small Outline Package (TC) 1Mx16 Synchronous DRAM 1.2(0.0472) 1.0(0.0394) 0.646 REF GAGE PLANE 0~5deg Rev. 4.0/Aug. 02 10.262(0.4040) 10.059(0.3960) 0.45(0.0177) 0.8(0.0315 BSC) 0.30(0.0118) 21.057(0.8290) 20.879(0.8220) 0.210(0.0083) 0.597(0.0235) 0.120(0.0118) 0.406(0.0160) HY57V161610D UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) ...