HY57V653220BTC-7 Hynix Semiconductor, HY57V653220BTC-7 Datasheet

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HY57V653220BTC-7

Manufacturer Part Number
HY57V653220BTC-7
Description
Manufacturer
Hynix Semiconductor
Datasheet

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ORDERING INFORMATION
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.1.6/Dec. 01
DESCRIPTION
The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
HY57V653220BTC-10P
HY57V653220BTC-55
HY57V653220BTC-10
HY57V653220BTC-5
HY57V653220BTC-6
HY57V653220BTC-7
HY57V653220BTC-8
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Part No.
Clock Frequency
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
100MHz
4 Banks x 512K x 32Bit Synchronous DRAM
Power
Normal
4Banks x 512Kbits
Organization
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
x32
Interface
LVTTL
HY57V653220B
400mil 86pin TSOP II
Package
1

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HY57V653220BTC-7 Summary of contents

Page 1

... ORDERING INFORMATION Part No. Clock Frequency HY57V653220BTC-5 200MHz HY57V653220BTC-55 183MHz HY57V653220BTC-6 166MHz HY57V653220BTC-7 143MHz HY57V653220BTC-8 125MHz HY57V653220BTC-10P 100MHz HY57V653220BTC-10 100MHz This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. ...

Page 2

PIN CONFIGURATION PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A10 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable DQM0~3 Data Input/Output Mask DQ0 ~ ...

Page 3

FUNCTIONAL BLOCK DIAGRAM 512Kbit x 4banks x 32 I/O Synchronous DRAM Self Refresh Logic & Timer CLK Row Active CKE CS RAS CAS WE Column DQM0 Active DQM1 DQM2 DQM3 Bank Select A0 Address A1 Register A10 BA0 BA1 Mode ...

Page 4

... V IH Input low voltage V IL Note : 1.All voltages are referenced 2.V V (min) is 3.15V for HY57V653220BTC-5/55/6 DD/ DDQ 3.V (max) is acceptable 5.6V AC pulse width with 3ns of duration with no input clamp diodes IH 4.V (min) is acceptable -2.0V AC pulse width with IL AC OPERATING CONDITION Parameter AC input high / low level voltage ...

Page 5

CAPACITANCE (TA=25 C, f=1MHz, VDD=3.3V) Parameter Input capacitance CLK A0 ~ A10, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 Data input / output capacitance DQ0 ~ DQ31 OUTPUT LOAD CIRCUIT Output DC Output Load Circuit DC CHARACTERISTICS I Parameter ...

Page 6

DC CHARACTERISTICS II Parameter Symbol Operating Current IDD1 IDD2P Precharge Standby Current in power down mode IDD2PS IDD2N Precharge Standby Current in non power down mode IDD2NS IDD3P Active Standby Current in power down mode IDD3PS IDD3N Active Standby Current ...

Page 7

AC CHARACTERISTICS I Parameter Symbol CAS Latency = 3 tCK3 System clock cycle time CAS Latency = 2 tCK2 Clock high pulse width tCHW Clock low pulse width tCLW CAS Latency = 3 tAC3 Access time from clock CAS Latency ...

Page 8

AC CHARACTERISTICS II Parameter Symbol Operation tRC RAS cycle time Auto Refresh tRRC RAS to CAS delay tRCD RAS active time tRAS RAS precharge time tRP RAS to RAS bank active delay tRRD CAS to CAS delay tCCD Write command ...

Page 9

DEVICE OPERATING OPTION TABLE HY57V653220B-5 CAS Latency 200MHz(5ns) 3CLKs 183MHz(5.5ns) 3CLKs 166MHz(6ns) 3CLKs HY57V653220B-55 CAS Latency 183MHz(5.5ns) 3CLKs 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs HY57V653220B-6 CAS Latency 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs 125MHz(8ns) 3CLKs HY57V653220B-7 CAS Latency 143MHz(7ns) 3CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs ...

Page 10

HY57V653220B-10 CAS Latency 100MHz(10ns) 3CLKs 83MHz(12ns) 2CLKs 66MHz(15ns) 2CLKs Rev.1.6/Dec. 01 tRCD tRAS tRC 2CLKs 5CLKs 7CLKs 2CLKs 5CLKs 7CLKs 2CLKs 4CLKs 6CLKs HY57V653220B tRP tAC tOH 2CLKs 6ns 2.5ns 2CLKs 6ns 2.5ns 2CLKs 6ns 2.5ns 10 ...

Page 11

COMMAND TRUTH TABLE Command Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-READ-Single-WRITE Entry 1 Self Refresh Exit Entry Precharge power down ...

Page 12

PACKAGE INFORMATION 400mil 86pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.50(0.0197) Rev.1.6/Dec. 01 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 0.150(0.0059) 0.050(0.0020) 5deg 0.21(0.008) 0deg 0.18(0.007) HY57V653220B Unit : mm(inch) 1.194(0.0470) 0.991(0.0390) 0.210(0.0083) 0.597(0.0235) 0.120(0.0047) 0.406(0.0160) 12 ...

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