HY5DU283222AF-4 Hynix Semiconductor, HY5DU283222AF-4 Datasheet
HY5DU283222AF-4
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HY5DU283222AF-4 Summary of contents
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... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon- sibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Jun. 2004 HY5DU283222AF HY5DU283222AF 1 ...
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... Changed IDD2N target specification 5) Changed tCK_max value of HY5DU283222AF-33/36 from 6ns to 10ns 0.4 Changed CAS Latency of HY5DU283222AF-28 from CL5 to CL4 0.5 Changed tRAS_max Value from 120K to 100K in All Frequency Insert Overshoot/ Under Specification 0 ...
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... DQ) ORDERING INFORMATION Part No. HY5DU283222AF-2 HY5DU283222AF-22 HY5DU283222AF-25 HY5DU283222AF-28 HY5DU283222AF-33 HY5DU283222AF-36 HY5DU283222AF-4 HY5DU283222AF-5 Rev. 0.7 / Jun. 2004 power supply • Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe power supply • All addresses and control inputs except Data, Data ...
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... VSS VDD VSS A10 VDD VDD NC BA1 A2 A11 A9 BA0 ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh HY5DU283222AF DQ29 DQ28 VSSQ DM3 DQ30 VDDQ NC VDDQ VSSQ VSSQ VSSQ DQ26 VSSQ VSS VDD VDDQ VSS VSSQ ...
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... DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU283222AF 5 ...
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... Rev. 0.7 / Jun. 2004 Write Data Register 2-bit Prefetch Unit 64 Bank 1Mx32/Bank0 Control 1Mx32 /Bank1 1Mx32 /Bank2 1Mx32 /Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU283222AF DQ[0:31] DQS(0~3) Data Strobe Transmitter Data Strobe DS Receiver 6 ...
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... If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.7 / Jun. 2004 CKEn CS RAS HY5DU283222AF A8/ CAS WE ADDR code code Note 1 1,4 X ...
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... Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 0.7 / Jun. 2004 /CS, /RAS, CKEn /CAS, / HY5DU283222AF A8/ DM(0~3) BA ADDR Note ...
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... BA OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU283222AF Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set DSEL NOP NOP NOP BST ILLEGAL ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222AF Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL ...
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... L BA OPCODE BA, CA, AP READ/READAP HY5DU283222AF Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter ROW ACT after tWR NOP ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222AF Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ...
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... HY5DU283222AF /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle X Exit power down, enter idle X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue power down mode ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU283222AF SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.7 / Jun. 2004 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DU283222AF < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 15 ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU283222AF AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Rev. 0.7 / Jun. 2004 CAS Latency BT A7 Test Mode 0 Normal Vendor 1 test mode A8 DLL Reset Yes CAS Latency Reserved Reserved Reserved Reserved Reserved HY5DU283222AF Burst Length Burst Length Sequential Reserved Reserved Reserved Reserved Reserved A3 Burst Type 0 Sequential 1 Interleave Interleave Reserved Reserved Reserved Reserved Reserved 17 ...
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... A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 0.7 / Jun. 2004 Sequential XX0 0, 1 XX1 1, 0 X00 X01 X10 X11 000 001 010 011 100 101 110 111 HY5DU283222AF Interleave ...
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... This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to- point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength. Rev. 0.7 / Jun. 2004 HY5DU283222AF 19 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 0.7 / Jun. 2004 RFU HY5DU283222AF DLL A0 DLL enable 0 Enable 1 Diable A1 Output Driver Impedance Control 0 RFU* 1 Half (60%) 0 RFU* 1 Weak (40%) 0 RFU* 1 Semi Half (50%) 0 RFU* ...
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... V TT REF V 0.49*V 0.5*V REF DDQ . DD may not exceed ± the DC value. o (TA Voltage referenced to V Symbol Min 0. =0V HY5DU283222AF Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2.5 2.625 V 2.8 2.95 V 2.5 2.625 V 2.8 2. 0.3 V DDQ - ...
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... RC OL (max), t =min (min), /CS ≥ V (min 140 (max), t =min (min), /CS ≥ V (min 190 (min), I =0mA CK OL 750 (min), RFC 400 3 1100 1000 HY5DU283222AF = 0V) SS Speed 210 190 180 170 160 150 230 210 200 190 180 170 130 120 110 100 ...
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... V + 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V -0.2 IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DU283222AF = 0V) SS Max Unit Note 0.35 V REF V + 0.6 V DDQ 0.5*V +0.2 V DDQ Value Unit V x 0.5 ...
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... The area between the overshoot signal and GND must be less than or equal to(See below Fig) Volt (v) Max. area = 2.4 v-nS Rev. 0.7 / Jun. 2004 Parameter + Time(nS) Parameter + Time(nS) HY5DU283222AF Specifications 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS Max. Amplitude = 1. Ground 5 6 Specifications 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS Max. Amplitude = 1. Ground ...
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... CL t -0.45 0. DQSCK -0.45 0.45 t DQSQ - 0.25 tHPmin -tQHS tCH min t QHS - 0. DQSH 0.45 0.55 t DQSL 0.45 0.55 t DQSS 0.85 1. 0.35 - tDSS 0.3 - HY5DU283222AF 22 25 Min Max Min Max 100K 12 100K 2 0.45 0.55 0.45 ...
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... RPST 0.4 0.6 0.4 t WPRES WPREH 0.35 - 0.35 t 0.4 0.6 0.4 WPST t MRD XSC 200 - 200 2tCK 2tCK t PDEX - + tIS + tIS t REFI - 7.8 - HY5DU283222AF 22 25 Unit Max Min Max 1.1 0.9 1.1 CK 0.6 0 0.6 0.4 0 200 - 2tCK ...
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... HY5DU283222AF 36 4 Max Min Max Min - 100K 8 100K ...
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... HY5DU283222AF Max Min Max Min - 0.75 - 0.75 - 0.75 - 0.75 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 1.15 0.85 1.15 0.85 - 0.4 - 0.45 - ...
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Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). ...
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... AC CHARACTERISTICS - II Frequency CL tRC 500MHz (2ns 450MHz (2.2ns 400MHz (2.5ns 350MHz (2.8ns 300MHz (3.3ns 275MHz (3.6ns 250MHz (4ns 200MHz (5ns Rev. 0.7 / Jun. 2004 tRFC tRAS tRCDRD HY5DU283222AF tRCDWR tRP tDAL Unit tCK tCK tCK tCK tCK tCK tCK tCK 30 ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 0.7 / Jun. 2004 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω T Zo=50Ω V REF C =30pF L HY5DU283222AF Symbol Min Max Unit ...
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... Ball Location ] Ball existing Optional (Vss thermal ball) Rev. 0.7 / Jun. 2004 1.2 mm max 0.76mm ± 0.05 12mm± 0.1 0.35mm ± 0.05 0.8mm Detailed “A” 8.8mm 0.12mm HY5DU283222AF Detailed “A” 0.5mm Diameter 0.55Max 0.45Min 32 ...